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AM62A7 Datasheet(PDF) 178 Page - Texas Instruments

Part # AM62A7
Description  AM62Ax Sitara™ Processors
PDF  238 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM62A7 Datasheet(HTML) 178 Page - Texas Instruments

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7.10.5.16.1.7 UHS–I SDR25 Mode
Table 7-92, Figure 7-78, Table 7-93, and Figure 7-79 present timing requirements and switching characteristics
for MMC0 – UHS-I SDR25 Mode.
Table 7-92. Timing Requirements for MMC0 – UHS-I SDR25 Mode
see Figure 7-78
NO.
MIN
MAX
UNIT
SDR251
tsu(cmdV-clkH)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
2.15
ns
SDR252
th(clkH-cmdV)
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
1.27
ns
SDR253
tsu(dV-clkH)
Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge
2.15
ns
SDR254
th(clkH-dV)
Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge
1.27
ns
MMC[ ]_CLK
x
MMC[ ]_CMD
x
MMC
DAT
[ ]_
[3:0]
x
SDR251
SDR252
SDR253
SDR254
Figure 7-78. MMC0 – UHS-I SDR25 – Receive Mode
Table 7-93. Switching Characteristics for MMC0 – UHS-I SDR25 Mode
see Figure 7-79
NO.
PARAMETER
MIN
MAX
UNIT
fop(clk)
Operating frequency, MMC0_CLK
50
MHz
SDR255
tc(clk)
Cycle time, MMC0_CLK
20
ns
SDR256
tw(clkH)
Pulse duration, MMC0_CLK high
9.2
ns
SDR257
tw(clkL)
Pulse duration, MMC0_CLK low
9.2
ns
SDR258
td(clkL-cmdV)
Delay time, MMC0_CLK rising edge to MMC0_CMD transition
2.4
8.1
ns
SDR259
td(clkL-dV)
Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition
2.4
8.1
ns
MMC[ ]_CLK
x
MMC
CMD
[ ]_
x
MMC
DAT
[ _
[3:0]
x]
SDR255
SDR257
SDR256
SDR258
SDR259
SDR258
SDR259
Figure 7-79. MMC0 – UHS-I SDR25 – Transmit Mode
AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1
SPRSP77A – MARCH 2023 – REVISED AUGUST 2023
www.ti.com
178
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1



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