AD4080BBCZ datasheet(32/95 Pages) AD

32 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

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and the starting address for the transaction are transmitted to the

AD4080. The instruction phase is immediately followed by a data

transaction phase during which one or more bytes of information

is exchanged between the host and the AD4080. This content is

framed by a continuous assertion of the interface chip select ( CS )

as illustrated in the generic timing presented in Figure 51 and

Figure 52.

Figure 51. Generic SPI Configuration Frame, CRC Disabled

Figure 52. Generic SPI Configuration Write Operation, CRC Enabled

SPI Register Interface

The configuration register interface is an SPI that enables both

device configuration and system status monitoring. This interface

is configured for 4-wire, full-duplex operation. Dedicated interface

pins for the interface chip select (CS), serial clock (SCLK), and

serial data input (SDI) are intended for direct connection to the host

controller. By default, at power-up or after a software reset, the

configuration interface SDO function is enabled and assigned to the

GPIO0 pin.

The configuration interface timing convention implemented in this

design is consistent with SPI Mode 3, clock polarity (CPOL) =

1, clock phrase (CPHA) = 1. As such, the serial clock (SCLK) is

expected to idle high and the state of the data pins, SDI and SDO,

are updated on the falling (leading) edge of the clock such that

these pin can be sampled on the subsequent rising (trailing) edge.

See the ADI Analog Dialogue, Introduction to SPI Interface article

for more details regarding the SPI and SPI modes.

The memory access controller associated with this interface sup-

ports a number of user-programmable options accessible through

the interface configuration memory space (Address 0x00 to Ad-

dress 0x11). The available options for the AD4080 are listed and

described in Table 14.

Table 14. Configuration Memory Controller Options Summary

Interface Option

Description

Software Reset (SW_RESET,

SW_RESETX)

Resets the internal configuration memory to the default state (except for ADDR_ASCENSION bit). Data FIFO is unaffected. Only use this

reset method once the ADC is in an idle state, where conversions are not clocked, and any existing conversion is completed. See the

Software Reset section for details.

Address Ascension

(ADDR_ASCENSION)

Selecting this option changes the behavior of the memory controller address counter from decrementing (default) to incrementing. This

change affects multibyte transfers, for example, when accessing a multibyte register as a single entity or when streaming mode is enabled.

The selection impacts the starting address for multibyte register accesses in strict register access mode. See the Address Ascension

Selection section for details.

Short Instruction

(SHORT_INSTRUCTION)

Selecting this option reduces the length of the address field in the instruction word from 15 bits to 7 bits.

Single Instruction

(SINGLE_INST)

Selecting this option changes from the default streaming mode to single instruction mode, which requires the host controller to transmit an

instruction for each register access within a given SPI frame. The size of an entity is dependent on the strict register access setting and

whether or not the register is multibyte. This feature allows random access to the memory space during configuration. See the Instruction

Mode Selection section for details.

Strict Register Access

(STRICT_REGISTER_ACCESS)

Selecting this option instructs the memory controller to treat a multibyte register as a single entity, generating a fault when a partial access

is attempted. See the Strict Access Selection and Multibyte Registers section for details.

CRC Enable (CRC_ENABLE,

CRC_ENABLEB)

Selecting this option enables a cyclic redundancy check (CRC) to verify the integrity of data sent to and received from the host. See the

Configuration Cyclical Redundancy Check (CRC) section for details.

Status Data Transmission

(SEND_STATUS)

Selecting this options enables the transmission of status data through the SDO line during the instruction phase of the data frame. See th

eStatus Data Transmission section for details.

AD4080BBCZ Datasheet(PDF) 32 Page - Analog Devices

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