AD4080BBCZ datasheet(44/95 Pages) AD

44 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. 0 | 44 of 95

Echo Clock Mode

In LVDS data interface mode, the DCO+ and DCO− pin pair

is an echo clock output that provides a buffered and delayed

version of CLK+ and CLK− pin pair, facilitating data clocking to

the host controller data clocking. This feature is controlled by the

LVDS_SELF_CLK_MODE bit in the ADC Data Interface Configura-

tion B register (see the ADC Data Interface Configuration B Regis-

ter section, Address 0x16). By default, echo clock mode is active

(LVDS_SELF_CLK_MODE = 0). Setting LVDS_SELF_CLK_MODE

= 1 disables the DCO+ and DCO− output driver, putting the device

in self clock mode (see the Self Clock Mode section) .

When echo clock mode is active, the interface requires a minimum

of three LVDS pairs (CLK+ and CLK−, DCO+ and DCO−, and DA+

and DA−) to be connected between the host controller and the

AD4080. A maximum of five LVDS pairs are required if the CNV+

and CNV− pin pair is configured as an LVDS input and the DB+ and

DB− data lane is enabled. The conversion clock (CNV+ and CNV−)

and data clock (CLK+ and CLK−) can be shared amongst multiple

AD4080 devices as long as care is taken to fanout the clock

network, such that the edge placement requirement is satisfied.

In echo clock mode, data from enabled lanes is clocked out in

sync to both rising and falling edges of DCO+ and DCO− in a

DDR scheme. Figure 72 and Figure 73 illustrate the relevant LVDS

interface timing with respect to the DCO+ and DCO− echo clock for

single lane and dual lane configurations, respectively. Calculation

of tMSB_READ is described in the ADC Result Latency and LVDS

Interface Alignment section.

Consider matching the data clock (DCO+ and DCO−) and data

lane (DA+ and DA−, DB+ and DB−) lane routing from the ADC to

the host processor for the physical layout to minimize timing skew,

which may affect data recovery in the host. For additional routing

suggestions, see the Layout Guidelines section.

Figure 72. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Echo Clock Mode

Figure 73. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Echo Clock Mode

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