AD4080BBCZ datasheet(46/95 Pages) AD

46 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. 0 | 46 of 95

LVDS Manchester Encoding Mode

This mode is accessed via the ADC_DATA_INTF_CONFIG_B reg-

ister (Address 0x16), which produces Manchester encoding of the

result data in compliance with IEEE 802.3. This mode can be

used in isolated data applications where the converter supplies can

be floated and the data outputs capacitively coupled to the host

controller. By ensuring that the mean output of each data lane is

0, the receiver side common-mode voltage is not disturbed by the

result pattern.

Manchester encoding is available in dual lane LVDS mode only so

that the maximum data throughput is achievable with the maximum

400 MHz LVDS clock rate.

Figure 76 shows an example how this isolation can be implement-

ed. Note that the LVDS 100 Ω termination resistor prior to the

isolation capacitors is required.

Figure 76. Isolated LVDS

ADC Result Latency and LVDS Interface

Alignment

WhenAD4080 is configured for LVDS interface mode, each conver-

sion result is placed into the LVDS interface output shift register(s).

The LVDS_CNV_CLK_CNT bits in the ADC Data Interface Config-

uration B register (see the ADC Data Interface Configuration B

in time when the conversion result data is loaded into the LVDS

interface output shift register(s). The total time from the rising

edge of a convert pulse to when the MSB of that conversion

request is internally available to transfer to the output register is

defined as (tCYC + tMSB), both specified in Table 2. Because the

transfer of this result data is under the control of the LVDS of

CLK+ and CLK−, there is an additional (1.5 × tCLK) that must

be allowed to guarantee a fully completed result is transferred to

the interface for read back. The user must calculate the correct

required LVDS_CNV_CLK_CNT value and configure the ADC Data

Interface Configuration B register (see the ADC Data Interface

Configuration B Register section) according to the conversion rate

and tCLK used.

For minimum latency, the correct LVDS_CNV_CLK_CNT value to

use for a particular conversion rate is calculated as (tMSB/tCLK +

1.5). This number is rounded down to the nearest integer value.

The maximum tMSB time is specified as 22.4 ns with gain error

correction enabled (see the Gain Error Correction section). For a

40 MSPS conversion rate in single lane LVDS with a 400 MHz

LVDS clock, this is calculated as 22.4 ns/2.5 ns + 1.5, yielding a

setting of 10 for the LVDS_CNV_CLK_CNT. Conversion latency is

then determined as time, aligned to the falling edge of the CLK

signal, described as tMSB_READ or latency in the timing diagram,

which can be calculated as (LVDS_CNV_CLK_CNT + 0.5) × tCLK.

For the given example, the single lane latency is calculated as (10 +

0.5) × 2.5 ns + tCYC = 46.25 ns latency.

Taking a dual lane example, the same formula is used, again taking

a 40 MSPS example, again with gain error correction enabled,

the LVDS clock runs at 200 MHz and yields (22.4 ns/5 ns) +

1.5, resulting in an LVDS_CNV_CLK_CNT of 5, and a total result

latency of (5 + 0.5) × 5 ns + tCYC = 52.5 ns latency.

Both of these examples are calculated to achieve the minimum

latency, and it is possible to use a higher LVDS_CNV_CLK_CNT

value, whereby latency is increased by tCLK for each +1 unit in-

crease in the LVDS_CNV_CLK_CNT value.

Figure 77 and Figure 78 serve as aids to describe the placement

of the ADC result data onto the LVDS interface controlled by the

LVDS_CNV_CLK_CNT. Figure 77 shows that a new result is inter-

nally completed after (tCYC + tMSB), and this result is now available

to the interface, signified here also by a notional tMSB_AVAILABLE

(introduced only for the purposes of the Figure 77 explanation).

As this example represents a 40 MSPS conversion rate, Figure 77

shows that the LVDS_CNV_CLK_CNT setting of 10 is the earliest

the conversion result can be loaded to the LVDS interface. One

additional full tCLK cycle is required (a complete cycle being CLK+

falling edge to next CLK+ falling edge) is required to move the MSB

to the output. This cycle is highlighted within Figure 77 also with a

notional tMSB_READ indicator for illustrative purposes only.

AD4080BBCZ Datasheet(PDF) 46 Page - Analog Devices

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