AD4080BBCZ datasheet(83/95 Pages) AD

83 / 95 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

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Rev. 0 | 83 of 95

Device Status Register

Address: 0x14, Reset: 0x09, Name: DEVICE_STATUS

Figure 123. Device Status Register

Table 47. Bit Descriptions for DEVICE_STATUS

Bits

Bit Name

Description

Reset

Access

FIFO_FULL

FIFO Full Status Flag.

0x0

0: FIFO Not Full.

1: FIFO Full.

FIFO_READ_DONE

FIFO Read Done Flag.

0x0

0: FIFO Read Not Done.

1: FIFO Read Done.

HI_STATUS

High Threshold Detection Status Flag. Writing 1 to this bit clears it.

0x0

R/W1C

0: High Threshold Event Not Detected.

1: High Threshold Event Detected.

LO_STATUS

Low Threshold Detection Status Flag. Writing 1 to this bit clears it.

0x0

R/W1C

0: Low Threshold Event Not Detected.

1: Low Threshold Event Detected.

POR_ANA_FLAG

POR Analog Status. Allows user to detect when an analog POR event occurs. An analog POR is triggered at

power-up or when the 1.1 V logic supply or ADC reference drops to less than the 2.7 threshold values or when

the user issues a software reset. Writing 1 to this bit clears it.

0x1

R/W1C

0: Analog POR Flag Cleared.

1: Analog POR Event Detected.

ADC_CNV_ERR

ADC Conversion Error Flag. Writing 1 to this bit clears it.

0x0

R/W1C

0: ADC Conversion Okay.

1: ADC Conversion Error. The user has breached the minimum tCONV specification, and the conversion results

are invalid. The user must ensure that the correct clock timing specifications are met.

ROM_CRC_ERR

ROM CRC/ECC Failure Flag.

0x0

0: ROM CRC Check Okay.

1: ROM CRC/ECC Failure.

POR_FLAG

POR Status. Allows user to detect when a POR event occurs. A POR is triggered at power-up or when the 1.1

V logic supply drops to less than the 0.93 V threshold value or when the user issues a software reset. Writing 1

to this bit clears it.

0x1

R/W1C

0: POR Flag Cleared.

1: POR Event Detected.

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