AD4080BBCZ datasheet(22/95 Pages) AD

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Data Sheet

AD4080

THEORY OF OPERATION

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Table 9. Integrated Supply Decoupling Summary (Continued)

Supply Pin

Nominal Value (μF)

Tolerance (%)

Return Path

VDD11

1.88 (4× 0.47)

±10

GND

IOVDD

0.22

±10

IOGND

INTERNALLY REGULATED SUPPLY

CONFIGURATION

The AD4080 includes two internal LDO regulators, one to generate

the 1.1 V VDD11 supply rail and another to internally generate the

1.1V IOVDD supply rail. Upon power on or reset of the AD4080

registers, both regulators automatically power up when an external

voltage source in the range of 1.4 V to 2.7 V is applied to the

VDDLDO pin. The regulators are designed to supply the internal

load requirement of the AD4080; therefore, no external loading is

permitted. Noted that, as described in the Power Saving Operating

Modes section, IOVDD is disabled in both power saving modes.

The required connectivity when using the internal regulators is

illustrated in Figure 37. As shown in Figure 37, the VDD11 pins

(A1, A2, and A3) must be shorted together. It is recommended that

a thick trace or polygon on the device side of the PCB be used

to implement this connection in the physical design to minimize

routing impedance. The VDD33 rail is supplied with an external

3.3 V supply. This supply can be removed when using power

saving modes. When this supply is removed, only analog circuity

is held in reset, and the configuration register content remains

unaffected. Refer to the Table 1 section for the applicable input

voltage tolerance for each supply rail.

Figure 37. Internally Regulated (1.1 V) Supply Configuration

The internally regulated configuration is ideal for use in area con-

strained applications where the ability to eliminate external regula-

tors is advantageous. However, noted that, in this configuration, the

internal supply regulation introduces additional power dissipation.

EXTERNALLY GENERATED SUPPLY

CONFIGURATION

In system using externally generated supplies VDDLDO must be

left unconnected. With VDDLDO unconnected both the internal

LDO powering VDD11 and the internal LDO powering IOVDDD are

automatically disabled. VDD11 must be connected to an externally

generated 1.1V supply rail and IOVDD should be connected to an

externally generated 1.1V to 1.2V supply rail. It should be noted

that if VDD11 is not present the part will be held in a POR state

and all AD4080 registers reset to their default state the after the

supply has been reestablished. More details on the POR circuitry

can be found in the Power-On Reset (POR) Monitor section. The

VDD33 rail is supplied with an external 3.3 V supply. The VDD33

supply can be removed to further reduce power in the Power

Saving Operating Modes, only analog circuity is in held in reset,

and the register content remains unaffected. Refer to Table 1 for the

applicable input voltage tolerance for each supply rail.

As illustrated in the example of Figure 38, external voltage sources

are applied to VDD11 and IOVDD pins.

Figure 38. Externally Sourced Supply Configuration

POWER-ON RESET (POR) MONITOR

The AD4080 power supply monitoring circuits inhibit the converter

functions and reset the configuration memory when supply con-

ditions are outside the specified operating limits. This function

ensures each device is in a deterministic state after power-up.

The power-on function is constructed from two independent voltage

monitors, the first measuring the core 1.1 V supply and a second

measuring the voltage at the reference input (REFIN). Each monitor

has its own comparator output that is used to decouple the analog

and digital block resets as shown in Figure 39.

Figure 39. Simplified Diagram of POR Circuit

The core VDD (1.1 V) supply monitor compares the VDD11 supply

voltage against a preset threshold of 0.93 V. If the supply voltage

falls to less than this threshold, a reset signal, POR_D, asserts.

The digital logic reset signal, DIG_RESET, is defined as the logical

combination of the POR_D signal and (logical AND) the compliment

of the SPI software reset function. When either the POR_D signal

(VDD11 < 0.93 V) or the SW RESET signal is asserted, the internal

digital circuitry is held in reset. When cleared, the contents of the

configuration registers are restored to the factory default settings.

AD4080BBCZ Datasheet(PDF) 22 Page - Analog Devices

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