AD4080BBCZ datasheet(86/95 Pages) AD

86 / 95 page

Data Sheet

AD4080

CONFIGURATION REGISTERS

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Rev. 0 | 86 of 95

Table 50. Bit Descriptions for ADC_DATA_INTF_CONFIG_C (Continued)

Bits

Bit Name

Description

Reset

Access

[6:4]

LVDS_VOD

LVDS Differential Output Voltage. The valid entries are 0b001, 0b010, and 0b100 for the differential voltages

of ~185 mV, ~240 mV, and ~325 mV, respectively. Writing an invalid value resets the differential voltage to its

default setting of ~240 mV. However, user can read back the value written to these bits.

0x2

R/W

[3:0]

RESERVED

Reserved. Write 0b0000 to these bits.

0x0

Power Control Register

Address: 0x18, Reset: 0x00, Name: PWR_CTRL

It is not recommended to write to this register.

Figure 127. Power Control Register

Table 51. Bit Descriptions for PWR_CTRL

Bits

Bit Name

Description

Reset

Access

[7:2]

RESERVED

Reserved. Write 0b000000 to these bits.

0x0

ANA_DIG_LDO_PD

VDD11 LDO Disable. Enable or disable the LDO that powers the VDD11 rail. It is not recommended to

write to this bit.

0x0

R/W

0: LDO Enabled.

1: LDO Disabled.

INTF_LDO_PD

IOVDD LDO Disable. Enable or disable the LDO that powers the IOVDD rail. It is not recommended to

write to this bit.

0x0

R/W

0: LDO Enabled.

1: LDO Disabled.

AD4080BBCZ Datasheet(PDF) 86 Page - Analog Devices

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