AD4080BBCZ datasheet(50/95 Pages) AD

50 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. 0 | 50 of 95

LVDS Output Differential Drive

The AD4080 supports selection of the LVDS output differential

voltage from one of three predetermined differential amplitudes

of ±185 mV p-p, ±240 mV p-p, and ±325 mV p-p assuming a

termination resistance of 100 Ω across the differential pair. The

output common-mode voltage of the LVDS drive is adjusted for

each selection automatically to ensure that the peak output voltage

remains within the IOVDD rail. The current default selection sets

the differential amplitude at ±240 mV p-p. The output differential

voltage can be modified by writing to the LVDS_VOD bits of the

ADC Data Interface Configuration C register (see the ADC Data

Interface Configuration C Register section, Address 0x17).

Data Interface Test Functions

Regardless of the selected output configuration, the AD4080 is

equipped with self test functions that enable verification of the

integrity of the data interface physical layer, including device pads,

PCB interconnect, and the host interface connections. An interface

check function is available setting a fixed, 20-bit data pattern mode

to output. Selection of this test function is made by writing to the

INTF_CHK_EN bit in the Data Interface Configuration A register

(see the ADC Data Interface Configuration A Register section,

Address 0x15).

By enabling the built-in test function, access to conversion results

is suspended; therefore, only use this function at either power-up or

during an idle period when conversion results are not required for

normal system function.

Refer to the ADC Result Latency and LVDS Interface Alignment

section for further information.

SPI DATA INTERFACE

SPI Data Interface Configuration

For applications that do not require the interface bandwidth of the

LVDS interface, such as when using asynchronous capture into the

result FIFO, the data interface can be reconfigured into a single

or quad lane, SPI data interface. In this configuration, the AD4080

outputs data on either one or four CMOS data lanes simultaneously

at serial clock rates up to 50 MHz. The result data is shifted out

serially on the falling edge of the interface clock (DCLK). In SPI

configuration, the AD4080 results can be read at interface rates up

to 200 MHz when using four SPI lanes.

To select the SPI configuration, program the DATA_INTF_MODE

bit of the Data Interface Configuration A register (see the ADC

Data Interface Configuration A Register section, Address 0x15) with

Binary Sequence 1’b1. Once configured for SPI mode, the AD4080

LVDS drivers are automatically disabled, including the echo clock

output (DCO+ and DCO−), preventing contention between LVDS

and CMOS functions. As a result, the LVDS_SELF_CLK_MODE

and LVDS_VOD settings no longer effect the operation of the data

interface and can be left at their power-on defaults or another con-

venient value. Because the driver is disabled, the DCO+ and DCO−

output pins can, therefore, be left disconnected in the hardware

design as these pins are unused.

As detailed in Table 22, the following LVDS pins are reconfigured as

CMOS input or outputs to realize the SPI data interface.

Table 22. LVDS/SPI Data Interface Pins Crossreference

LVDS Pin

CMOS Pin

Function

CLK+

DCLK

Data interface clock input

CLK−

DCS

Data interface chip select input

DA+

SDOA

Serial Data Output A

DA−

SDOB

Serial Data Output B

DB+

SDOC

Serial Data Output C

DB−

SDOD

Serial Data Output D

As with LVDS configuration mode, SPI configuration selection al-

lows control of the number of active lanes. For SPI data interface

configuration, the user has the option to configure single lane SPI

or quad lane SPI.

SPI Active Data Lane Count

The SPI can be configured to output the result data on either one

or four data lanes, which is controlled by the SPI_LVDS_LANES

bit in the ADC Interface Configuration A register (see the ADC

Data Interface Configuration A Register section, Address 0x15). By

default, this bit is set to 0 (one lane active), and can be set to

1 to use four data lanes. Note that this bit also sets the number

of active data lanes for the LVDS interface. The data order and

pin assignment to the serial data output (SDOx) pins is detailed in

Table 23, and shown in Figure 86.

Table 23. SPI Data Lane(s) Data Order and Pin Assignment

Serial Data Output Pin

Output Data Order

One Active SPI Lane

(SPI_LVDS_LANES = 0)

Four Active SPI Lanes

(SPI_LVDS_LANES = 1)

SDOA

Not applicable

SDO 3

SDOB

SDO 0

SDO 2

SDOC

Not applicable

SDO 1

SDOD

Not applicable

SDO 0

Data Interface CRC

To ensure the integrity of the result data, a CRC is appended

to the FIFO results. This CRC is always enabled and appended.

The computation of the result checksum is independent of that of

the configuration interface. The result is 24 bits in length and is

appended to each data result record acquired from the FIFO.

Sign Extension

When accessing the FIFO data with the SPI data interface, the

20-bit resolution of the AD4080 is not a convenient length for

interfacing with microcontroller or microprocessor hosts. To make

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