AD4080BBCZ datasheet(21/95 Pages) AD

21 / 95 page

Data Sheet

AD4080

THEORY OF OPERATION

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Rev. 0 | 21 of 95

REFERENCE BUFFER AND COMMON-MODE

OUTPUT

The AD4080 integrates a charge reservoir capacitor (CREF) and a

low-drift reference buffer at the reference input pin (REFIN), elimi-

nating the need for dedicated external components and enabling

multiple AD4080 devices to share a single voltage reference.

The integrated capacitor (CREF) has a capacitance of 9.4 μF ± 20%,

and it is constructed from commercially available, multilayer, high

dielectric (X6S), ceramic capacitors. CREF serves as the primary

charge reservoir for the data converter. Integrated, in-package com-

ponents, such as CREF, minimize the overall solution area, mitigate

potential performance errors introduced by factors like component

selection, placement and routing challenges, and in general, reduce

the engineering effort to first design success.

Additional external capacitance (CRSV) can be placed across the

REFIN and REFGND pins for improved charge capacity and noise

rejection as required. As with all precision circuits, the placement

of the external reference capacitors must be as close to the device

pins as possible on the same side of the PCB. The routing between

the capacitor and device pins must minimize the series impedance

in each routing path.

Figure 35. REFIN and CMO Internal Equivalent Circuit and Typical

Application

The AD4080 internally generates a common-mode reference volt-

age of one-half of VREFIN, which is output through the CMO pin. The

absolute error in the CMO output voltage is guaranteed to be less

than ±20 mV. The CMO output is used to set the common-mode

output voltage of the analog front-end stage driving the AD4080

inputs, ensuring the AD4080 common-mode input requirement is

satisfied. The CMO output must be filtered with a RC LPF to limit

the total output noise as illustrated in Figure 35 (see RCMF and

CCMF).

The output is generated using a resistive divider connected to the

reference buffer output. The resulting output impedance at the CMO

pin is typically 700 Ω. Due to the limited drive capability at the

CMO pin, the external load must be carefully considered to avoid

excessive start-up times or absolute errors. The CMO output may

be directly connected to a high impedance common-mode input

of a fully differential amplifier driving the AD4080, assuming the

charging time for the preceding noise limiting filter does not impact

the start-up time required for the application. In general, consider

CMO buffering for the following situations:

►

The VDD33 power rail of the AD4080 is frequently cycled.

►

Short start-up settling times are required.

►

If the external load on CMO exceeds 30 μA (RL < 45 kΩ). See

Figure 25 for the typical load regulation information.

POWER SUPPLIES

The power requirements for the AD4080 are distributed across a

minimum of three supply domains including a 3.3 V analog circuit

domain (VDD33), a 1.1 V core supply (VDD11), and a 1.1 V

domain for the digital interface (IOVDD). An optional fourth supply

rail (VDDLDO) can be used to supply power to two integrated

voltage regulator used to internally power the 1.1 V core (VDD11)

and interface (IOVDD) rails. Each of these two regulators can be

independently turned off by software. For all details and design

considerations when using the internal voltage regulators, see the

Internally Regulated Supply Configuration section. On the other

hand, for applications that will not use internal regulators see

the Externally Generated Supply Configuration section for further

details.

Power for the VDD33 supply rail must be supplied from an external

source and must only be applied once power is supplied to the 1.1

V supply rails as described in the Power Supply Sequence section.

Figure 36. Typical Regulator Start-Up Transient, Converter Idle

All supply domains are internally decoupled using multilayer, high

dielectric, ceramic capacitors (X6S), eliminating the need of exter-

nal decoupling capacitors. However, care must be taken to under-

stand the bulk decoupling requirements for other components in the

design which share the same supply. Integrated supply decoupling

capacitors in the AD4080 are listed Table 6 as well as in Table 9.

Table 9. Integrated Supply Decoupling Summary

Supply Pin

Nominal Value (μF)

Tolerance (%)

Return Path

VDD33

0.47

±10

GND

VDDLDO

0.22

±10

GND

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