AD4080BBCZ datasheet(23/95 Pages) AD

23 / 95 page

Data Sheet

AD4080

THEORY OF OPERATION

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Rev. 0 | 23 of 95

The reference monitor compares the input voltage at the reference

input pin, REFIN, against a preset threshold of 2.7 V. As illustrated

in Figure 39, power for the reference monitor circuit is supplied from

the VDD33 supply. For correct operation of the monitor circuit, the

VDD33 supply must be applied to the AD4080 within the specified

tolerance of 3.3 V ± 5% before the reference source is enabled.

Assuming the device is operating within the specified supply condi-

tions, a reference voltage less than 2.7 V results in the assertion

of an internal reset signal, POR_A. The POR_A signal and (logical

AND) the DIG_RESET signal are combined to produce a reset

(ANA_RESET) for the analog circuit blocks including the ADC core,

ADC timer, reference buffer, etc. If this reset signal is asserted, the

analog blocks are placed in an inactive state, and the converter

functionality is disabled. This event is indicated with a value of 1 in

the POR_ANA_FLAG bit from the Device Status Register (Address

0x14). The state of the event detection is persistent until a Logic 1

is written to the POR_ANA_FLAG bit to clear the detection state.

POWER SUPPLY SEQUENCE

Table 10 specifies the recommended supply sequences for both

internal and external generation of 1.1 V supply rails (IOVDD and

VDD11). Both methods are shown in Figure 40 and Figure 41,

where highlighted in blue are the supplies that must be provided

to the AD4080, including the REFIN voltage. In both cases, the

AD4080 requires that the supplies are applied in ascending voltage

order. The design must also ensure that voltage is applied at the

analog inputs (IN+ and IN−) and reference input (REFIN) concur-

rently with or immediately following the VDD33 supply. As described

in the Power-On Reset (POR) Monitor section, the voltage at the

reference input pin must only be applied once VDD33 is within the

specified supply tolerance to avoid undesired behavior. Therefore, if

the selected voltage reference does not provide an enable pin, it is

strongly recommended to design the reference circuit to power up

after VDD33.

The configuration SPI inputs, CS, SCLK, and SDI, are protected

with clamps to the VDD33 supply rail to allow the inputs to swing

more than IOVDD. As a consequence of this architectural decision,

it is necessary to drive the SPI inputs to ground or to otherwise

leave the inputs floating until VDD33 is greater than IOVDD − 0.3

V. Alternatively, the VDD33 source can be connected to the device

using a series power switch, like the ADP199, configured so that

the switch is open when the source is less than IOVDD − 0.3 V,

eliminating the parasitic current path through the digital inputs to

VDD33.

Table 10. Recommended Supply Sequence

1.1 V Supplies (IOVDD and VDD11) Source

Supply Sequence

Internally Generated

1. VDDLDO

2. VDD33

3. Digital inputs

4. Input drive, reference

Externally Generated

1. IOVDD, VDD11

2. VDD33

3. Digital inputs

4. Input drive, reference

To power down the application circuit, the power-up sequence

specified in Table 10 should be reversed.

Figure 40. Power Supply Sequence, Internally Generated IOVDD, VDD11

AD4080BBCZ Datasheet(PDF) 23 Page - Analog Devices

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