AD4080BBCZ datasheet(19/95 Pages) AD

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Data Sheet

AD4080

THEORY OF OPERATION

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TRANSFER FUNCTION

The AD4080 digitizes the full-scale difference voltage of 2 × VREFIN

into 220 levels, resulting in an LSB size of 5.72 μV with VREFIN = 3.0

V. Note that 1 LSB at 20 bits is approximately 0.95 ppm.

Table 7 summarizes the mapping of input voltages to differential

output codes.

Figure 32. ADC Ideal Transfer Function for the Differential Output Codes

(FSR Is Full-Scale Range)

Table 7. Input Voltage to Output Code Mapping

Description

Analog Input Voltage

Difference (IN+ − IN−,

Volts)

Digital Output Code (Twos

Complement, Hex)

FS − 1 LSB

+VREFIN × (1 − 1/219)

0x7FFFF

Midscale + 1 LSB +VREFIN/219

0x00001

Midscale

0x00000

Midscale − 1 LSB −VREFIN/219

0xFFFFF

−FS + 1 LSB

−VREFIN × (1 − 1/219)

0x80001

−FS

−VREFIN

0x80000

EASY DRIVE ANALOG INPUTS

The AD4080 signal input consists of a fully differential input pair

(IN+ and IN−), each connected to the input sampling network

(series resistance (RS) and sampling capacitance (CS)) and a pair

of auxiliary inputs (AUXIN+ and AUXIN−) that provide a reference

to the sampling network linearization circuits. An equivalent circuit

model of the analog input is presented in Figure 33.

Figure 33. Equivalent Analog Input Circuit Model

In this model, the input sampling network was simplified to consist

of two ideal switches, RS and CS, for the ADC in acquisition mode.

The typical values for CS is 23.5 pF and RS is 26 Ω.

The parasitic capacitance related to the pin connection, CPIN, is

modeled as a shunt capacitor between the pin and device ground

terminal (GND). The capacitance includes parasitic capacitance

formed from the physical interface, routing in the package substrate

and the device input protection circuits. The CPIN value is typically

4.5 pF. The input protection circuit for the AD4080 is modeled as

diode clamps to the GND and VDD33 supply rails.

The external low-pass filters (LPFs) constructed from RFILTIN and

CFILTIN and RFILTAUX and CFILTAUX are band-limiting filters for the

primary and auxiliary paths, respectively.

The combination of RFILTIN and CFILTIN are often referred to as

anti-aliasing filters because these filters do introduce a single-pole

filter in the analog input signal path. However, the function of CFILTIN

is more complex and must be carefully considered. Conversion

through a SAR involves sampling the voltage from an internal ca-

pacitor, represented by CS in the Figure 33, which typically occurs

in two phases in time ϕ1 and ϕ2 . During the first phase, the ϕ1

switches are closed, the ϕ2 switches are opened, and the sampling

capacitors (CS) are charged to the analog input voltages present at

IN+ and IN−. During the second phase, the ϕ1 switches are opened,

the ϕ2 are closed, and the ADC converts the voltage onto CS.

Another short time phase exists, where the CS charge is reset after

the conversion is complete. This process repeats for each new

ADC conversion. The transfer of charge from the ADC analog input

pins to CS, due to the closing of the switches in each conversion

cycle, creates a demand at the analog input pin. It is important to

ensure that the voltage presented at the input pin is undisturbed by

the internal ADC activity so that the voltage can be converted with

the highest accuracy. Each new conversion presents a disturbance,

or kick, at the input. The faster the ADC conversion rate is, the

more frequent the occurrence of these kicks. An ADC driver is used

to ensure that the input voltage, disturbed by the kick at each sam-

pling instance, is fully settled to the required ADC resolution prior

to the next sample being acquired. The ADC driver amplifier must

have a wide enough output bandwidth to settle the voltage in time

for each sample, which creates a signal chain design constraint to

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