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AD4080BBCZ Datasheet(PDF) 92 Page - Analog Devices |
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AD4080BBCZ Datasheet(HTML) 92 Page - Analog Devices |
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92 / 95 page  Data Sheet AD4080 CONFIGURATION REGISTERS analog.com Rev. 0 | 92 of 95 Event Detection High Threshold Configuration Register Address: 0x21 and Address: 0x22, Reset: 0x0000, Name: EVENT_DETECTION_HI Figure 134. Event Detection High Threshold Configuration Register Table 58. Bit Descriptions for EVENT_DETECTION_HI Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. Write 0b0000 to these bits. 0x0 R [11:0] HI_THRESHOLD High Threshold Value. Twos complement data format where LSB = 1.46484 mV. 0x800 represents −2048 × LSB, and 0x7FF represents +2047 × LSB. 0x0 R/W Event Detection Low Threshold Configuration Register Address: 0x23 and Address: 0x24, Reset: 0x0000, Name: EVENT_DETECTION_LO Figure 135. Event Detection Low Threshold Configuration Register Table 59. Bit Descriptions for EVENT_DETECTION_LO Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. Write 0b0000 to these bits. 0x0 R [11:0] LO_THRESHOLD Low Threshold Value. Twos complement data format where LSB = 1.46484 mV. 0x800 represents −2048 × LSB, and 0x7FF represents +2047 × LSB. 0x0 R/W Offset Correction Register Address: 0x25 and Address: 0x26, Reset: 0x0000, Name: OFFSET Figure 136. Offset Correction Register Table 60. Bit Descriptions for OFFSET Bits Bit Name Description Reset Access [15:12] RESERVED Reserved. Write 0b0000 to this bit field. 0x0 R [11:0] OFFSET Offset Correction Coefficient. Twos complement data format where LSB = 0.00572 mV. 0x800 represents −2048 × LSB, and 0x7FF represents +2047 × LSB. 0x0 R/W |
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