AD4080BBCZ datasheet(39/95 Pages) AD

39 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. 0 | 39 of 95

the host controller is required for all subsequent serial transactions

according to the conditions described in Table 18. If used, enable

and validate the CRC function before writing to any of the device

configuration registers. To validate the CRC function is enabled,

follow the CRC configuration write with a SPI frame consisting of a

read of both the Interface Configuration C register and the Interface

Status A register using a valid checksum for the read transaction. If

enabled, the register contents for the CRC_ENABLE and CRC_EN-

ABLEB bits must be 1 and 10, respectively, and the CRC_ERR bit

in the Interface Status A register remains cleared (Logic 0). Once

confirmed, proceed with programming the remaining configuration

registers.

Table 18. Host Controller (SDI) Conditional Checksum Requirement

Summary

Command SINGLE_INST Bit Value

Check Sum Requirement

Write

Streaming (0) or single

instruction (1)

After each data register payload

Read

Streaming (0)

After the first register data payload

following the instruction phase

Single instruction (1)

After each data register payload

The following CRC-8 polynomial is implemented in the AD4080 to

compute the checksum for each register transaction:

x8 + x2 + x + 1

Each serial transaction is processed through this polynomial to

generate the checksum on a per register basis. The data and seed

values used for each checksum calculation are a function of the ac-

cess command (read/write); ADDR_ASCENSION, STRICT_REG-

ISTER_ACCESS, and SINGLE_INST settings; and the location of

the register data in the data stream as summarized in Table 19.

All register write access operations, regardless of SINGLE_INST

setting, require a valid CRC checksum to be sent from the host

following the data payload for each register. For multibyte registers,

if STRICT_REGISTER_ACCESS = 1, a valid CRC is appended to

the data stream after all bytes of the addressed register are sent.

If STRICT_REGISTER_ACCESS is cleared (0), each byte transmit-

ted must be followed by a valid checksum using the computation

rules that are described as follows.

For read access, the computation and transmission of a valid

checksum from the host is required to validate the command and

starting address only. In streaming mode (SINGLE_INST = 0),

a CRC checksum is sent from the host controller after the first

in streaming mode with padding data. The AD4080 continues to

produce valid checksum values after each register read to allow

validation in the host using the preceding data. As a new instruction

phase is required for each register accessed in single instruction

mode, a valid host CRC checksum is required for each register

accessed.

In single instruction mode (SINGLE_INST = 1), the polynomial

is computed for each register using the default seed value of

0xA5, the instruction phase data, and depending on the access

command, the desired register or padding data. In streaming mode

(SINGLE_INST = 0), the checksum computation for the first register

in the data stream is computed as if single instruction mode were

selected. Each subsequent register access checksum computation

is seeded with the starting address for the current register and the

corresponding data. Note that the starting address for multibyte reg-

isters changes with the ADDR_ASCENSION selection, assuming

the register access restriction is enabled (STRICT_REGISTER_AC-

CESS = 1). As previously described, the memory convention dic-

tates that if ADDR_ASCENSION is set to 0, the address for the

least significant byte of the multibyte register serves as the starting

address. Conversely, if the ADDR_ASCENSION bit is set to 1, the

address of the most significant byte of the multibyte register is

used.

Table 19. Configuration CRC Checksum Source Data Summary vs. SINGLE_INST and SPI Command

Command

Checksum

Source

Single Instruction Mode (SINGLE_INST = 1) or

Streaming Mode First CRC

Streaming Mode (SINGLE_INST = 0) after first CRC

Data Source

Seed

Data Source

Seed

Write

Controller

Instruction and data

0xA5

Current start address

AD4080

Instruction and data

Current start address

Read

Controller

Instruction and padding data

0xA5

Not required, send padding data

AD4080

Instruction and register content

Current start address

Figure 58. Streaming Mode Configuration with CRC Enabled, ADDR_ASCENSION = 1

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