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CLRC63201T/0FE Datasheet(PDF) 50 Page - NXP Semiconductors |
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CLRC63201T/0FE Datasheet(HTML) 50 Page - NXP Semiconductors |
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50 / 163 page ![]() Philips Semiconductors Product Specification Rev. 3.0; May 2003 Multiple Protocol Contactless Reader IC CL RC632 50 Confidential 5.2.4.8 ClockQControl Register controls clock generation for the 90° phase shifted Q-channel clock. Name: ClockQControl Address: 0x1F Reset value: 000XXXXX, 0xXX 7 6 5 4 3 2 1 0 ClkQ180Deg ClkQCalib 0 ClkQDelay Access Rights r r/w r/w dy dy dy dy dy Description of the bits Bit Symbol Function 7 ClkQ180Deg If the Q-clock is phase shifted more than 180° compared to the I-clock, the bit ClkQ180Deg is set to 1, otherwise it is 0. 6 ClkQCalib If this bit is 0, the Q-clock is calibrated automatically after the Reset Phase and after data reception from the card. If this bit is set to 1, no calibration is performed automatically. 5 0 This value shall not be changed 4-0 ClkQDelay This register shows the number of delay elements actually used to generate a 90°phase shift of the I-clock to obtain the Q-clock. It can be written directly by the µ-Processor or by the automatic calibration cycle. |
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