CLRC63201TSLASH0FE datasheet(80/163 Pages) PHILIPS

80 / 163 page

Philips Semiconductors

Product Specification Rev. 3.0; May 2003

Multiple Protocol Contactless Reader IC

CL RC632

Confidential

FIFO BUFFER

7.1

Overview

An 8x64 bit FIFO buffer is implemented in the CL RC632 acting as a parallel-to-parallel converter. It buffers

the input and output data stream between the µ-Processor and the internals of the CL RC632. Thus, it is

possible to handle data streams with lengths of up to 64 bytes without taking timing constraints into account.

7.2

Accessing the FIFO Buffer

7.2.1

ACCESS RULES

The FIFO-buffer input and output data bus is connected to the FIFOData Register. Writing to this register

stores one byte in the FIFO-buffer and increments the internal FIFO-buffer write-pointer. Reading from this

buffer read-pointer. The distance between the write- and read-pointer can be obtained by reading the

FIFOLength Register.

When the µ-Processor starts a command, the CL RC632 may, while the command is in progress, access the

FIFO-buffer according to that command. Physically only one FIFO-buffer is implemented, which can be used

in input- and output direction. Therefore the µ-Processor has to take care, not to access the FIFO-buffer in

an unintended way.

The following table gives an overview on FIFO access during command processing:

µ-Processor is allowed to

Active Command

Write to FIFO

Read from FIFO

Remark

StartUp

Idle

Transmit

Receive

Transceive

µ-Processor has to know the actual state of the command

(transmitting or receiving)

WriteE2

ReadE2

The µ-Processor has to prepare the arguments,

afterwards only reading is allowed

LoadKeyE2

LoadKey

Authent1

Authent2

LoadConfig

CalcCRC

Table 7-1: Allowed Access to the FIFO-Buffer

CLRC63201T/0FE Datasheet(PDF) 80 Page - NXP Semiconductors

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