CLRC63201TSLASH0FE datasheet(11/163 Pages) PHILIPS

11 / 163 page

Philips Semiconductors

Product Specification Rev. 3.0; May 2003

Multiple Protocol Contactless Reader IC

CL RC632

Confidential

3.2

Pin Description

Pin Types: I...Input;

O...Output;

PWR...Power

SYMBOL

TYPE

DESCRIPTION

OSCIN

Crystal Oscillator Input: input to the inverting amplifier of the oscillator.

This pin is also the input for an externally generated clock (fosc = 13.56 MHz).

IRQ

Interrupt Request: output to signal an interrupt event

MFIN

MIFARE Interface Input: accepts a digital, serial data stream according to

ISO14443A (MIFARE)

MFOUT

MIFARE Interface Output: delivers a serial data stream according to ISO14443A

(MIFARE)

•CODE Interface Output: delivers a serial data stream according to I•CODE1 and

ISO 15693

TX1

Transmitter 1: delivers the modulated 13.56 MHz energy carrier

TVDD

PWR

Transmitter Power Supply: supplies the output stage of TX1 and TX2

TX2

Transmitter 2: delivers the modulated 13.56 MHz energy carrier

TVSS

PWR

Transmitter Ground: supplies the output stage of TX1 and TX2

NCS

Not Chip Select: selects and activates the µ-Processor interface of the CL RC632

NWR

Not Write: strobe to write data (applied on D0 to D7) into the CL RC632 register

R/NW

Read Not Write: selects if a read or write cycle shall be performed.

nWrite

Not Write: selects if a read or write cycle shall be performed

NRD

Not Read: strobe to read data from the CL RC632 register (applied on D0 to D7)

NDS

Not Data Strobe: strobe for the read and the write cycle

nDStrb

Not Data Strobe: strobe for the read and the write cycle

DVSS

PWR

Digital Ground

Master In Slave Out (MISO), SPI interface,

D0 to D7

I/O

8 Bit Bi-directional Data Bus

…

AD0 to AD7

I/O

8 Bit Bi-directional Address and Data Bus

ALE

Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch

when HIGH.

Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch

when HIGH.

nAStrb

Not Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch

when LOW.

NSS

Not Slave Select: strobe for the SPI communication

Address Line 0: Bit 0 of register address

nWait

Not Wait: signals with LOW that an access-cycle may started and with HIGH that it

may be finished.

MOSI

Master Out Slave In, SPI interface

PIN Description (continued)

1 These pins offer different functionality according to the selected µ-Processor interface type. For detailed

information, refer to chapter 4.

2 The SL RC400 uses the name SIGOUT for the MFOUT pin. The CLRC 632 functionality includes the test possibilities

for the SL RC 400 using the pin MFOUT

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