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CLRC63201T/0FE Datasheet(PDF) 93 Page - NXP Semiconductors |
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CLRC63201T/0FE Datasheet(HTML) 93 Page - NXP Semiconductors |
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93 / 163 page  Philips Semiconductors Product Specification Rev. 3.0; May 2003 Multiple Protocol Contactless Reader IC CL RC632 93 Confidential 10 POWER REDUCTION MODES 10.1 Hard Power Down A Hard Power Down is enabled with HIGH on pin RSTPD. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a certain value. This is shown in the following table. SYMBOL PIN TYPE DESCRIPTION OSCIN 1 I Not separated from input, pulled to AVSS IRQ 2 O High impedance MFIN 3 I Separated from Input MFOUT 4 O LOW HIGH, if TX1RFEn=1 TX1 5 O LOW, if TX1RFEn=0 HIGH, only if TX2RFEn=1 and TX2Inv=0 TX2 7 O LOW NWR 9 I Separated from Input NRD 10 I Separated from Input NCS 11 I Separated from Input D0 to D7 13 to 20 I/O Separated from Input ALE 21 I Separated from Input A0 22 I/O Separated from Input A1 23 I Separated from Input A2 24 I Separated from Input AUX 27 O High impedance RX 29 I Not changed VMID 30 A Pulled to AVDD RSTPD 31 I Not changed OSCOUT 32 O HIGH Table 10-1: Signal on Pins during Hard Power Down 10.2 Soft Power Down The Soft Power Down-mode is entered immediately by setting bit PowerDown in the Control-Register. All internal current sinks are switched off (including the oscillator buffer). In difference to the Hard Power Down-mode, the digital input-buffers are not separated by the input pads and keep their functionality. The digital output pins do not change their state. After resetting bit PowerDown in the Control-Register it needs 512 clocks until the Soft Power Down mode is left indicated by the PowerDown bit itself. Resetting it does not immediately clear it. It is cleared automatically by the CL RC632 when the Soft Power Down-Mode is left. Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and it will take a certain time tosc until the oscillator is stable and the clock cycles can be detected by the internal logic. |
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