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CLRC63201T/0FE Datasheet(PDF) 20 Page - NXP Semiconductors |
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CLRC63201T/0FE Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 163 page  Philips Semiconductors Product Specification Rev. 3.0; May 2003 Multiple Protocol Contactless Reader IC CL RC632 20 Confidential 5 CL RC632 REGISTER SET 5.1 CL RC632 Registers Overview Page Addresshex Register Name Function 0 Page selects the register page 1 Command starts (and stops) the command execution 2 FIFOData in- and output of 64 byte FIFO buffer 3 PrimaryStatus status flags of the receiver and transmitter and of the FIFO buffer 4 FIFOLength number of bytes buffered in the FIFO 5 SecondaryStatus diverse status flags 6 InterruptEn control bits to enable and disable passing of interrupt requests 7 InterruptRq interrupt request flags 8 Page selects the register page 9 Control diverse control flags e.g.: timer, power saving A ErrorFlag error flags showing the error status of the last command executed B CollPos bit position of the first bit collision detected on the RF-interface C TimerValue actual value of the timer D CRCResultLSB LSB of the CRC-Coprocessor register E CRCResultMSB MSB of the CRC-Coprocessor register F BitFraming adjustments for bit oriented frames 10 Page selects the register page 11 TxControl controls the logical behaviour of the antenna driver pins TX1 and TX2 12 CWConductance selects the conductance of the antenna driver pins TX1 and TX2 13 ModConductance Defines the driver output conductance 14 CoderControl sets the clock rate and the coding mode 15 ModWidth selects the width of the modulation pulse 16 ModWidthSOF selects the width of the modulation pulse for SOF (I •CODE Fast-Mode) 17 TypeBFraming Defines the framing for ISO14443-B communication 18 Page selects the register page 19 RxControl1 controls receiver behaviour 1A DecoderControl controls decoder behaviour 1B BitPhase selects the bit-phase between transmitter and receiver clock 1C RxThreshold selects thresholds for the bit decoder 1D BPSKDemControl Control BPSK receiver behaviour 1E RxControl2 controls decoder behaviour and defines the input source for the receiver 1F ClockQControl controls clock generation for the 90° phase shifted Q-channel clock CL RC632 Register Set (continued) |
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