CLRC63201TSLASH0FE datasheet(95/163 Pages) PHILIPS

95 / 163 page

Philips Semiconductors

Product Specification Rev. 3.0; May 2003

Multiple Protocol Contactless Reader IC

CL RC632

Confidential

11 START UP PHASE

The phases executed during the start up are shown in the following figure.

11.1 Hard Power Down Phase

The Hard Power Down Phase is active during the following cases:

•

Power On Reset caused by power up at pin DVDD

(active while DVDD is below the digital reset threshold)

•

Power On Reset caused by power up at pin AVDD

(active while AVDD is below the analog reset threshold)

•

A HIGH level on pin RSTPD

(active while pin RSTPD is HIGH)

11.2 Reset Phase

The Reset Phase follows the Hard Power Down Phase automatically. One’s the oscillator is running stable, it

takes 512 clocks. During the Reset Phase, some of the register bits are pre-set by hardware. The respective

reset values are given in the description of each register (see 5.2.).

Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and that it will

take a certain time tosc until the oscillator is stable.

11.3 Initialising Phase

The Initialising Phase follows the Reset Phase automatically. It takes 128 clocks. During the Initialising

Phase the content of the E²PROM blocks 1 and 2 is copied into the registers 10hex to 2Fhex. (see 6.3)

Note: At production test, the CL RC632 is initialised with default configuration values. This reduces the

µ-Processors effort for configuring the device to a minimum.

Hard Power

Down Phase

Reset Phase

Initialising

Phase

Ready

Start Up Phase

Reset

Init

States

Figure 11-1: Start Up Procedure

CLRC63201T/0FE Datasheet(PDF) 95 Page - NXP Semiconductors