M24M02E-F datasheet(25/54 Pages) STMICROELECTRONICS

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6.4.1

Random address read

A dummy write is first performed to load the address into this address counter (as shown in Figure 17. Read

mode sequences) but without sending a stop condition. Then, the bus controller sends another start condition,

and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the

contents of the addressed byte. The bus controller must not acknowledge the byte, and terminates the transfer

with a stop condition.

6.4.2

Current address read

For the current address read operation, following a start condition, the bus controller sends only a device select

code with the RW bit set to 1. The device acknowledges this and outputs the byte addressed by the internal

address counter. The counter is then incremented. The bus controller terminates the transfer with a stop

condition, as shown in Figure 17. Read mode sequences, without acknowledging the byte.

Note:

The address counter value is defined by instructions accessing either the memory, registers, or the identification

page. When accessing the registers or the identification page, the address counter value is loaded with the byte

location, therefore the next current address read in the memory uses this new address counter value. When

accessing the memory, it is safer to always use the random address read instruction (this instruction loads the

address counter with the byte location to read in the memory, see Section 6.4.1: Random address read) instead

of the current address read instruction.

6.4.3

Sequential read

This operation can be used after a current address read or a random address read. The bus controller does

acknowledge the data byte output and sends additional clock pulses so that the device continues to output the

next byte in sequence. To terminate the stream of bytes, the bus controller must not acknowledge the last byte,

and must generate a stop condition, as shown in Figure 17. Read mode sequences.

The output data comes from consecutive addresses, with the internal address counter automatically incremented

after each byte output. After the last memory address, the address counter rolls-over, and the device continues to

output data from the memory address 00h.

M24M02E-F

Instructions

DS14157 - Rev 2

page 25/54

M24M02E-F Datasheet(PDF) 25 Page - STMicroelectronics