PIC18F6X2X datasheet(27/386 Pages) MICROCHIP

27 / 386 page

 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 25

PIC18F6X2X/8X2X

2.6.1

SYSTEM CLOCK SWITCH BIT

The system clock source switching is performed under

software control. The system clock switch bits,

SCS1:SCS0

(OSCCON<1:0>),

control

the

clock

switching. When the SCS0 bit is ‘0’, the system clock

source comes from the main oscillator that is selected

by the FOSC configuration bits in CONFIG1H Configu-

ration register. When the SCS0 bit is set, the system

clock source will come from the Timer1 oscillator. The

SCS0 bit is cleared on all forms of RESET.

When FOSC bits are programmed for Software PLL

mode, SCS1 bit can be used to select between primary

oscillator/clock and PLL output. SCS1 bit will only have

an effect on the system clock if the PLL is enabled

(PLLEN = 1) and locked (LOCK = 1), else it will be

forced cleared. When programmed with Configuration

Controlled PLL, SCS1 bit will be forced clear.

OSCCON REGISTER

Note:

The Timer1 oscillator must be enabled

and operating to switch the system clock

source. The Timer1 oscillator is enabled

by setting the T1OSCEN bit in the Timer1

Control register (T1CON). If the Timer1

oscillator is not enabled, then any write to

the SCS0 bit will be ignored (SCS0 bit

forced cleared) and the main oscillator will

continue to be the system clock source.

U-0

R/W-0

—

LOCK

PLLEN

SCS1

SCS0

bit 7

bit 0

bit 7-4

Unimplemented: Read as ‘0’

bit 3

LOCK: Phase Lock Loop Lock Status bit

= Phase lock loop output is stable as system clock

= Phase lock loop output is not stable and output cannot be used as system clock

bit 2

PLLEN(1): Phase Lock Loop Enable bit

= Enable phase lock loop output as system clock

= Disable phase lock loop

bit 1

SCS1: System Clock Switch bit 1

When PLLEN and LOCK bits are set:

= Use PLL output

= Use primary oscillator/clock input pin

When PLLEN or LOCK bit is cleared:

Bit is forced clear.

bit 0

SCS0(2): System Clock Switch bit 0

When OSCSEN configuration bit = 0 and T1OSCEN bit = 1:

= Switch to Timer1 oscillator/clock pin

= Use primary oscillator/clock input pin

When OSCSEN and T1OSCEN are in other states:

Bit is forced clear.

Note 1: PLLEN bit is forced set when configured for ECIO+PLL and HS+PLL. This bit is

writable for ECIO+SPLL and HS+SPLL modes only; forced cleared for all other

Oscillator modes.

2: The setting of SCS0 = 1 supersedes SCS1 = 1.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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