PIC18F6X2X datasheet(96/386 Pages) MICROCHIP

96 / 386 page

PIC18F6X2X/8X2X

DS39612A-page 94

Advance Information

 2003 Microchip Technology Inc.

9.2

PIR Registers

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are three Peripheral Interrupt

Flag registers (PIR1, PIR2 and PIR3).

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

2: User software should ensure the appropri-

ate interrupt flag bits are cleared prior to

enabling an interrupt and after servicing

that interrupt.

R/W-0

R-0

R/W-0

PSPIF(1)

ADIF

RC1IF

TX1IF

SSPIF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

bit 7

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

= A read or a write operation has taken place (must be cleared in software)

= No read or write has occurred

Note 1: Enabled only in Microcontroller mode for PIC18F8X2X devices.

bit 6

ADIF: A/D Converter Interrupt Flag bit

= An A/D conversion completed (must be cleared in software)

= The A/D conversion is not complete

bit 5

RC1IF: USART1 Receive Interrupt Flag bit

= The USART1 receive buffer, RCREGx, is full (cleared when RCREGx is read)

= The USART1 receive buffer is empty

bit 4

TX1IF: USART Transmit Interrupt Flag bit

= The USART1 transmit buffer, TXREGx, is empty (cleared when TXREGx is written)

= The USART1 transmit buffer is full

bit 3

SSPIF: Master Synchronous Serial Port Interrupt Flag bit

= The transmission/reception is complete (must be cleared in software)

= Waiting to transmit/receive

bit 2

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared in software)

= TMR1 register did not overflow

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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