PIC18F6X2X datasheet(75/386 Pages) MICROCHIP

75 / 386 page

 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 73

PIC18F6X2X/8X2X

6.0

EXTERNAL MEMORY

INTERFACE

The external memory interface is a feature of the

PIC18F8X2X devices that allows the controller to

access external memory devices (such as FLASH,

EPROM, SRAM, etc.) as program or data memory.

The physical implementation of the interface uses 27

pins. These pins are reserved for external address/data

bus functions; they are multiplexed with I/O port pins on

four ports. Three I/O ports are multiplexed with the

address/data bus, while the fourth port is multiplexed

with the bus control signals. The I/O port functions are

enabled when the EBDIS bit in the MEMCON register

is set (see Register 6-1). A list of the multiplexed pins

and their functions is provided in Table 6-1.

As implemented in the PIC18F8X2X devices, the inter-

face operates in a similar manner to the external

memory interface introduced on PIC18C601/801

microcontrollers. The most notable difference is that

the interface on PIC18F8X2X devices only operates in

16-bit modes. The 8-bit mode is not supported.

For a more complete discussion of the operating

modes that use the external memory interface, refer to

Section 4.1.1, “PIC18F6X2X/8X2X Program Memory

Modes”.

6.1

Program Memory Modes and the

External Memory Interface

As previously noted, PIC18F8X2X controllers are

capable of operating in any one of four Program Mem-

ory modes using combinations of on-chip and external

program memory. The functions of the multiplexed port

pins depends on the Program Memory mode selected,

as well as the setting of the EBDIS bit.

In Microprocessor Mode, the external bus is always

active and the port pins have only the external bus

function.

In Microcontroller Mode, the bus is not active and

the pins have their port functions only. Writes to the

MEMCOM register are not permitted.

In Microprocessor with Boot Block or Extended

Microcontroller Mode, the external program memory

bus shares I/O port functions on the pins. When the

device is fetching or doing table read/table write oper-

ations on the external program memory space, the

pins will have the external bus function. If the device is

fetching and accessing internal program memory loca-

tions only, the EBDIS control bit will change the pins

from external memory to I/O port functions. When

EBDIS = 0, the pins function as the external bus.

When EBDIS = 1, the pins function as I/O ports.

MEMCON REGISTER

Note:

The

external

memory

interface

not

implemented on PIC18F6X2X (64-pin) devices.

R/W-0

U-0

R/W-0

U-0

R/W-0

EBDIS

—WAIT1

WAIT0

—

—WM1

WM0

bit7

bit0

bit 7

EBDIS: External Bus Disable bit

= External system bus disabled, all external bus drivers are mapped as I/O ports

= External system bus enabled and I/O ports are disabled

bit 6

Unimplemented: Read as ‘0’

bit 5-4

WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits

= Table reads and writes will wait 0 TCY

= Table reads and writes will wait 1 TCY

= Table reads and writes will wait 2 TCY

= Table reads and writes will wait 3 TCY

bit 3-2

Unimplemented: Read as ‘0’

bit 1-0

WM1:WM0: TBLWRT Operation with 16-bit Bus bits

= Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when

TABLAT<1> written

= Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB)

will activate

= Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate

Note:

The MEMCON register is unimplemented and reads all ‘0’s when the device is in

Microcontroller mode.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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