Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

PIC18F6X2X Datasheet(PDF) 78 Page - Microchip Technology

Part # PIC18F6X2X
Description  64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
PDF  386 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F6X2X Datasheet(HTML) 78 Page - Microchip Technology

Back Button PIC18F6X2X Datasheet HTML 74Page - Microchip Technology PIC18F6X2X Datasheet HTML 75Page - Microchip Technology PIC18F6X2X Datasheet HTML 76Page - Microchip Technology PIC18F6X2X Datasheet HTML 77Page - Microchip Technology PIC18F6X2X Datasheet HTML 78Page - Microchip Technology PIC18F6X2X Datasheet HTML 79Page - Microchip Technology PIC18F6X2X Datasheet HTML 80Page - Microchip Technology PIC18F6X2X Datasheet HTML 81Page - Microchip Technology PIC18F6X2X Datasheet HTML 82Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 78 / 386 page
background image
PIC18F6X2X/8X2X
DS39612A-page 76
Advance Information
 2003 Microchip Technology Inc.
6.2.2
16-BIT WORD WRITE MODE
Figure 6-2 shows an example of 16-bit Word Write
mode for PIC18F8X2X devices. This mode is used for
word-wide memories which includes some of the
EPROM and FLASH type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory, and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWT cycles to even or odd addresses.
During
a
TBLWT
cycle
to
an
even
address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is tri-
stated for the data portion of the bus cycle. No write
signals are activated.
During
a
TBLWT
cycle
to
an
odd
address
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSbit of the TBLPTR but it is left unconnected.
Instead, the UB and LB signals are active to select both
bytes. The obvious limitation to this method is that the
table write must be done in pairs on a specific word
boundary to correctly write a word location.
FIGURE 6-2:
16-BIT WORD WRITE MODE EXAMPLE
AD<7:0>
PIC18F8X2X
AD<15:8>
ALE
373
A<20:1>
373
OE
WRH
A<19:16>
A<x:0>
D<15:0>
OE
WR(1)
CE
D<15:0>
JEDEC Word
EPROM Memory
Address Bus
Data Bus
Control Lines
Note
1:
This signal only applies to table writes. See Section 5.1, “Table Reads and Writes”.
CE



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com