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PIC18F6X2X Datasheet(PDF) 78 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 78 Page - Microchip Technology |
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78 / 386 page ![]() PIC18F6X2X/8X2X DS39612A-page 76 Advance Information 2003 Microchip Technology Inc. 6.2.2 16-BIT WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8X2X devices. This mode is used for word-wide memories which includes some of the EPROM and FLASH type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses. During a TBLWT cycle to an even address (TBLPTR<0> = 0), the TABLAT data is transferred to a holding latch and the external address data bus is tri- stated for the data portion of the bus cycle. No write signals are activated. During a TBLWT cycle to an odd address (TBLPTR<0> = 1), the TABLAT data is presented on the upper byte of the AD15:AD0 bus. The contents of the holding latch are presented on the lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is unused. The signal on the BA0 pin indicates the LSbit of the TBLPTR but it is left unconnected. Instead, the UB and LB signals are active to select both bytes. The obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. FIGURE 6-2: 16-BIT WORD WRITE MODE EXAMPLE AD<7:0> PIC18F8X2X AD<15:8> ALE 373 A<20:1> 373 OE WRH A<19:16> A<x:0> D<15:0> OE WR(1) CE D<15:0> JEDEC Word EPROM Memory Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 5.1, “Table Reads and Writes”. CE |
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