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PIC18F6X2X Datasheet(PDF) 37 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 37 Page - Microchip Technology |
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37 / 386 page  2003 Microchip Technology Inc. Advance Information DS39612A-page 35 PIC18F6X2X/8X2X FSR1H PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu FSR1L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6X2X PIC18F8X2X N/A N/A N/A POSTINC2 PIC18F6X2X PIC18F8X2X N/A N/A N/A POSTDEC2 PIC18F6X2X PIC18F8X2X N/A N/A N/A PREINC2 PIC18F6X2X PIC18F8X2X N/A N/A N/A PLUSW2 PIC18F6X2X PIC18F8X2X N/A N/A N/A FSR2H PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu FSR2L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu STATUS PIC18F6X2X PIC18F8X2X ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6X2X PIC18F8X2X 0000 0000 uuuu uuuu uuuu uuuu TMR0L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F6X2X PIC18F8X2X ---- 0000 ---- 0000 ---- uuuu LVDCON PIC18F6X2X PIC18F8X2X --00 0101 --00 0101 --uu uuuu WDTCON PIC18F6X2X PIC18F8X2X ---- ---0 ---- ---0 ---- ---u RCON(4) PIC18F6X2X PIC18F8X2X 0--1 11qq 0--1 qquu u--1 qquu TMR1H PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6X2X PIC18F8X2X 0-00 0000 u-uu uuuu u-uu uuuu TMR2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6X2X PIC18F8X2X 1111 1111 1111 1111 1111 1111 T2CON PIC18F6X2X PIC18F8X2X -000 0000 -000 0000 -uuu uuuu SSPBUF PIC18F6X2X PIC18F8X2X xxxx xxxx uuuu uuuu uuuu uuuu SSPADD PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu SSPSTAT PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu SSPCON1 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu SSPCON2 PIC18F6X2X PIC18F8X2X 0000 0000 0000 0000 uuuu uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ‘0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’. 7: If MCLR function is disabled, PORTG<5> is a read only bit. |
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