PIC18F6X2X datasheet(55/386 Pages) MICROCHIP

55 / 386 page

 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 53

PIC18F6X2X/8X2X

TABLE 4-3:

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details

on page:

TOSU

—

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000

34, 44

TOSH

Top-of-Stack High Byte (TOS<15:8>)

0000 0000

34, 44

TOSL

Top-of-Stack Low Byte (TOS<7:0>)

0000 0000

34, 44

STKPTR

STKFUL

STKUNF

—

Return Stack Pointer

00-0 0000

34, 45

PCLATU

—

bit 21

Holding Register for PC<20:16>

--10 0000

34, 46

PCLATH

Holding Register for PC<15:8>

0000 0000

34, 46

PCL

PC Low Byte (PC<7:0>)

0000 0000

34, 46

TBLPTRU

—

—bit 21(2)

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

--00 0000

34, 71

TBLPTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

34, 71

TBLPTRL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

0000 0000

34, 71

TABLAT

Program Memory Table Latch

0000 0000

34, 71

PRODH

Product Register High Byte

xxxx xxxx

34, 87

PRODL

Product Register Low Byte

xxxx xxxx

34, 87

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

34, 91

INTCON2

RBPU

INTEDG0

INTEDG1

INTEDG2

INTEDG3

TMR0IP

INT3IP

RBIP

1111 1111

34, 92

INTCON3

INT2IP

INT1IP

INT3IE

INT2IE

INT1IE

INT3IF

INT2IF

INT1IF

1100 0000

34, 93

INDF0

Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)

n/a

POSTINC0

Uses contents of FSR0 to address data memory - value of FSR0 post-incremented

(not a physical register)

n/a

POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented

(not a physical register)

n/a

PREINC0

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)

n/a

PLUSW0

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented

(not a physical register) - value of FSR0 offset by value in WREG

n/a

FSR0H

—

Indirect Data Memory Address Pointer 0 High Byte

---- 0000

34, 58

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

xxxx xxxx

34, 58

WREG

Working Register

xxxx xxxx

INDF1

Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)

n/a

POSTINC1

Uses contents of FSR1 to address data memory - value of FSR1 post-incremented

(not a physical register)

n/a

POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented

(not a physical register)

n/a

PREINC1

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)

n/a

PLUSW1

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented

(not a physical register) - value of FSR1 offset by value in WREG

n/a

FSR1H

—

Indirect Data Memory Address Pointer 1 High Byte

---- 0000

35, 58

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx

35, 58

BSR

—

Bank Select Register

---- 0000

35, 57

INDF2

Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)

n/a

POSTINC2

Uses contents of FSR2 to address data memory - value of FSR2 post-incremented

(not a physical register)

n/a

POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented

(not a physical register)

n/a

Legend:

= unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other

Oscillator modes.

Bit 21 of the TBLPTRU allows access to the device configuration bits.

These registers are unused on PIC18F6X2X devices; always maintain these clear.

RG5 is available only if MCLR function is disabled in configuration.

PIC18F6X2X Datasheet(PDF) 55 Page - Microchip Technology

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