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PIC18F6X2X Datasheet(PDF) 95 Page - Microchip Technology

Part # PIC18F6X2X
Description  64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
PDF  386 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F6X2X Datasheet(HTML) 95 Page - Microchip Technology

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 2003 Microchip Technology Inc.
Advance Information
DS39612A-page 93
PIC18F6X2X/8X2X
REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
bit 7
bit 0
bit 7
INT2IP: INT2 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 6
INT1IP: INT1 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 5
INT3IE: INT3 External Interrupt Enable bit
1
= Enables the INT3 external interrupt
0
= Disables the INT3 external interrupt
bit 4
INT2IE: INT2 External Interrupt Enable bit
1
= Enables the INT2 external interrupt
0
= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1
= Enables the INT1 external interrupt
0
= Disables the INT1 external interrupt
bit 2
INT3IF: INT3 External Interrupt Flag bit
1
= The INT3 external interrupt occurred (must be cleared in software)
0
= The INT3 external interrupt did not occur
bit 1
INT2IF: INT2 External Interrupt Flag bit
1
= The INT2 external interrupt occurred (must be cleared in software)
0
= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1
= The INT1 external interrupt occurred (must be cleared in software)
0
= The INT1 external interrupt did not occur
Legend:
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.



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