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PIC18F6X2X Datasheet(PDF) 80 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 80 Page - Microchip Technology |
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80 / 386 page ![]() PIC18F6X2X/8X2X DS39612A-page 78 Advance Information 2003 Microchip Technology Inc. 6.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 6-4 through Figure 6-6. FIGURE 6-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) FIGURE 6-5: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q4 Q4 Q4 Q4 ALE OE 3AABh WRH WRL AD<15:0> BA0 CF33h Opcode Fetch MOVLW 55h from 007556h 9256h 0E55h ‘1’ ‘1’ ‘1’ ‘1’ Table Read of 92h from 199E67h 1 TCY Wait Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Apparent Q Actual Q A<19:16> 0Ch 00h CE ‘0’ ‘0’ Memory Cycle Instruction Execution TBLRD Cycle1 TBLRD Cycle2 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 A<19:16> ALE OE AD<15:0> CE Opcode Fetch Opcode Fetch Opcode Fetch TBLRD* TBLRD Cycle1 ADDLW 55h from 000100h Q2 Q1 Q3 Q4 0Ch CF33h TBLRD 92h from 199E67h 9256h from 000104h Memory Cycle Instruction Execution INST(PC-2) TBLRD Cycle2 MOVLW 55h from 000102h MOVLW |
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