PIC18F6X2X datasheet(85/386 Pages) MICROCHIP

85 / 386 page

 2003 Microchip Technology Inc.

Advance Information

DS39612A-page 83

PIC18F6X2X/8X2X

7.3

Reading the Data EEPROM

Memory

To read a data memory location, the user must write the

address to the EEADRH:EEADR register pair, clear the

EEPGD control bit (EECON1<7>), clear the CFGS

control bit (EECON1<6>), and then set the RD control

bit (EECON1<0>). The data is available for the very

next instruction cycle; therefore, the EEDATA register

can be read by the next instruction. EEDATA will hold

this value until another read operation or until it is

written to by the user (during a write operation).

EXAMPLE 7-1:

DATA EEPROM READ

7.4

Writing to the Data EEPROM

Memory

To write an EEPROM data location, the address must

first be written to the EEADRH:EEADR register pair

and the data written to the EEDATA register. Then the

sequence in Example 7-2 must be followed to initiate

the write cycle.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. It is strongly

recommended that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable writes. This mechanism prevents accidental

writes to data EEPROM due to unexpected code

execution (i.e., runaway programs). The WREN bit

should be kept clear at all times except when updating

the

EEPROM.

The

WREN

bit

not

cleared

by hardware

After a write sequence has been initiated, EECON1,

EEADRH, EEADR and EEDATA cannot be modified.

The WR bit will be inhibited from being set unless the

WREN bit is set. The WREN bit must be set on a pre-

vious instruction. Both WR and WREN cannot be set

with the same instruction.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EEPROM Write Complete

Interrupt Flag bit (EEIF) is set. The user may either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

EXAMPLE 7-2:

DATA EEPROM WRITE

MOVLW

DATA_EE_ADDRH

;

MOVWF

EEADRH

; Upper bits of Data Memory Address to read

MOVLW

DATA_EE_ADDR

;

MOVWF

EEADR

; Lower bits of Data Memory Address to read

BCF

EECON1, EEPGD

; Point to DATA memory

BCF

EECON1, CFGS

; Access EEPROM

BSF

EECON1, RD

; EEPROM Read

MOVF

EEDATA, W

; W = EEDATA

MOVLW

DATA_EE_ADDRH

;

MOVWF

EEADRH

; Upper bits of Data Memory Address to write

MOVLW

DATA_EE_ADDR

;

MOVWF

EEADR

; Lower bits of Data Memory Address to write

MOVLW

DATA_EE_DATA

;

MOVWF

EEDATA

; Data Memory Value to write

BCF

EECON1, EEPGD

; Point to DATA memory

BCF

EECON1,CFGS

; Access EEPROM

BSF

EECON1, WREN

; Enable writes

BCF

INTCON, GIE

; Disable Interrupts

MOVLW

55h

;

Required

MOVWF

EECON2

; Write 55h

Sequence

MOVLW

AAh

;

MOVWF

EECON2

; Write AAh

BSF

EECON1, WR

; Set WR bit to begin write

BSF

INTCON, GIE

; Enable Interrupts

; User code execution

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

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