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PIC18F6X2X Datasheet(PDF) 57 Page - Microchip Technology |
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PIC18F6X2X Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 386 page  2003 Microchip Technology Inc. Advance Information DS39612A-page 55 PIC18F6X2X/8X2X CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 36, 243 TMR3H Timer3 Register High Byte xxxx xxxx 36, 147 TMR3L Timer3 Register Low Byte xxxx xxxx 36, 147 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 36, 147 PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 36, 131 SPBRG1 USART1 Baud Rate Generator 0000 0000 36, 219 RCREG1 USART1 Receive Register 0000 0000 36, 226 TXREG1 USART1 Transmit Register 0000 0000 36, 224 TXSTA1 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 36, 216 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 36, 217 EEADRH — — — — — — EE Adr Register High ---- --00 36, 85 EEADR Data EEPROM Address Register 0000 0000 36, 85 EEDATA Data EEPROM Data Register 0000 0000 36, 85 EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 36, 85 EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 36, 82 IPR3 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 37, 102 PIR3 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 37, 96 PIE3 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 37, 99 IPR2 —CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 37, 101 PIR2 —CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 37, 95 PIE2 —CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 37, 98 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 37, 100 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 37, 94 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 37, 97 MEMCON(3) EBDIS —WAIT1 WAIT0 — —WM1 WM0 0-00 --00 37, 73 TRISJ(3) Data Direction Control Register for PORTJ 1111 1111 37, 129 TRISH(3) Data Direction Control Register for PORTH 1111 1111 37, 126 TRISG — — — Data Direction Control Register for PORTG ---1 1111 37, 121 TRISF Data Direction Control Register for PORTF 1111 1111 37, 118 TRISE Data Direction Control Register for PORTE 1111 1111 37, 115 TRISD Data Direction Control Register for PORTD 1111 1111 37, 112 TRISC Data Direction Control Register for PORTC 1111 1111 37, 110 TRISB Data Direction Control Register for PORTB 1111 1111 37, 107 TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 37, 123 LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 37, 129 LATH(3) Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 37, 126 LATG — — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 37, 123 LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 37, 121 LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 37, 118 LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 37, 115 LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 37, 112 LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 37, 110 LATA —LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 37, 107 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other Oscillator modes. 2: Bit 21 of the TBLPTRU allows access to the device configuration bits. 3: These registers are unused on PIC18F6X2X devices; always maintain these clear. 4: RG5 is available only if MCLR function is disabled in configuration. |
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