PIC16F18323-ESLASHRFQTP datasheet(113/442 Pages) MICROCHIP

113 / 442 page

 2015 Microchip Technology Inc.

Preliminary

DS40001799A-page 113

PIC16(L)F18313/18323

10.4.3

NVMREG WRITE TO EEPROM

Writing to the EEPROM is accomplished by the

following steps:

Set the NVMREGS and WREN bits of the

NVMCON1 register.

Write the desired address (address + 7000h)

into the NVMADRH:NVMADRL register pair

(Table 10-2).

Perform the unlock sequence as described in

Section 10.4.2 “NVM Unlock Sequence”

A single EEPROM word is written with NVMDATA. The

operation includes an implicit erase cycle for that word

(it is not necessary to set the FREE bit), and requires

many instruction cycles to finish. CPU execution

continues in parallel and, when complete, WR is

cleared by hardware, NVMIF is set, and an interrupt will

occur if NVMIE is also set. Software must poll the WR

bit to determine when writing is complete, or wait for the

interrupt to occur. WREN will remain unchanged.

Once the EEPROM write operation begins, clearing the

WR bit will have no effect; the operation will continue to

run to completion.

10.4.4

NVMREG ERASE OF PROGRAM

FLASH MEMORY

Before writing to Program Flash Memory, the word(s) to

be written must be erased or previously unwritten. Pro-

gram Flash Memory can only be erased one row at a

time. No automatic erase occurs upon the initiation of

the write to Program Flash Memory.

To erase a Program Flash Memory row:

Clear the NVMREGS bit of the NVMCON1

locations, or set the NMVREGS bit to erase

User ID locations.

Write

the

desired

address

into

the

NVMADRH:NVMADRL

pair

(Table 10-2).

Set the FREE and WREN bits of the NVMCON1

Perform the unlock sequence as described in

Section 10.4.2 “NVM Unlock Sequence”

the

Program

Flash

Memory

address

write-protected, the WR bit will be cleared and the

erase operation will not take place.

While erasing Program Flash Memory, CPU operation

is suspended, and resumes when the operation is

complete. Upon completion, the NVMIF is set, and an

interrupt will occur if the NVMIE bit is also set.

Write latch data is not affected by erase operations,

and WREN will remain unchanged.

FIGURE 10-3:

NVM ERASE

FLOWCHART

Start Erase Operation

Select Memory:

PFM,Config Words, User ID

(NVMREGS)

Select Word Address

(NVMADRH:NVMADRL)

Select Erase Operation

(FREE = 1)

Enable Write/Erase Operation

(WREN = 1)

End Erase Operation

Disable Interrupts

(GIE = 0)

Unlock Sequence

CPU stalls while Erase operation

completes (2ms typical)

Enable Interrupts

(GIE = 1)

Disable Write/Erase Operation

(WREN = 0)

Figure 10-2

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