DRV8876PWPR datasheet(14/51 Pages) TI2

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IOUT

VOUT

Control

Input

ITRIP

Re-enable

IOUT

VOUT

Control

Input

ITRIP

tOFF

DRV8876

SLVSDS7B – AUGUST 2019 – REVISED NOVEMBER 2019

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7.3.3.2.1

Fixed Off-Time Current Chopping

In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON)

for tOFF duration after IOUT exceeds ITRIP. After tOFF the outputs are re-enabled according to the control inputs

unless IOUT is still greater than ITRIP. If IOUT is still greater than ITRIP, the H-bridge will enter another period of

brake/low-side slow decay for tOFF. If the state of the EN/IN1 or PH/IN2 control pin inputs changes during the tOFF

time, the remainder of the tOFF time is ignored, and the outputs will again follow the inputs.

The fixed off-time mode allows for a simple current chopping scheme without involvement from the external

controller. This is shown in Figure 12. Fixed off-time mode will support 100% duty cycle current regulation since

the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the

EN/IN1 or PH/IN2 pins to reset the outputs.

Figure 12. Off-Time Current-Regulation

7.3.3.2.2

Cycle-By-Cycle Current Chopping

In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON)

after IOUT exceeds ITRIP until the next control input edge on the EN/IN1 or PH/IN2 pins. This allows for additional

control of the current chopping scheme by the external controller. This is shown in Figure 13. Cycle-by-cycle

mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the

outputs after the brake, low-side slow decay state has been entered.

Figure 13. Cycle-By-Cycle Current Regulation

In cycle-by-cycle mode, the device will also indicates whenever the H-bridge has entered internal current

chopping by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from

the control inputs or the load has reached the ITRIP threshold. This is shown in Figure 14. nFAULT will be

released whenever the next control input edge is received by the device and the outputs are reset.

DRV8876PWPR Datasheet(PDF) 14 Page - Texas Instruments