DRV8876PWPR datasheet(22/51 Pages) TI2

22 / 51 page

6.0 mm

Trace 0.22 mm x 34.5 mm

at 0.65-mm pitch

2.46 mm

PTH via at 1.2 mm

Drill diameter = 300 m;

plating = 25 m

DRV8876

SLVSDS7B – AUGUST 2019 – REVISED NOVEMBER 2019

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•

Mid layer 2: power plane, no thermal connection.

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Bottom layer: signal layer with small copper pad underneath DRV887x and thermally connected through

via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the

package (5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied. Thermal vias

are only present under the thermal pad (grid pattern with 1.2mm spacing).

Figure 19 shows an example of the simulated board for the HTSSOP package. Table 9 shows the dimensions of

the board that were varied for each simulation.

Figure 19. HTSSOP PCB model top layer

Table 9. Dimension A for 16-pin PWP package

Cu area (mm2)

Dimension A (mm)

17.0

22.8

31.0

42.8

VQFN (RGT package)

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2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness.

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Top layer: DRV887x VQFN package footprint.

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Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV887x. Bottom

layer copper area is varied in simulation. Thermal vias are only present under the thermal pad (grid

DRV8876PWPR Datasheet(PDF) 22 Page - Texas Instruments