DRV8876PWPR datasheet(17/51 Pages) TI2

17 / 51 page

136 k

68 k

5 V

44 k

156 k

5 V

100 k

DRV8876

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SLVSDS7B – AUGUST 2019 – REVISED NOVEMBER 2019

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7.3.5 Pin Diagrams

7.3.5.1 Logic-Level Inputs

Figure 15 shows the input structure for the logic-level input pins EN/IN1, PH/IN2, and nSLEEP.

Figure 15. Logic-Level Input

7.3.5.2 Tri-Level Inputs

Figure 16 shows the input structure for the tri-level input pin PMODE.

Figure 16. PMODE Tri-Level Input

7.3.5.3 Quad-Level Inputs

Figure 17 shows the input structure for the quad-level input pin IMODE.

Figure 17. Quad-Level Input

7.4 Device Functional Modes

The DRV887x family of devices have several different modes of operation depending on the system inputs.

7.4.1 Active Mode

After the supply voltage on the VM pin has crossed the undervoltage threshold VUVLO, the nSLEEP pin is logic

high, and tWAKE has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and

internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and current

control modes (IMODE) will be latched when the device enters active mode.

DRV8876PWPR Datasheet(PDF) 17 Page - Texas Instruments