TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-18
Signal Name
Shared Signal
Ball
Type Description – TCC763/ TCC764
GPIO_A[0]
SDO0 / FGPIO[0]
C9
I/O
GPIO_A[0] / General purpose serial I/O 0 Serial Data Output
FGPIO[0]
GPIO_B[29:28]
USBH_DN, USBH_DP
M9,L8
I/O
GPIO_B[29:28] / USBH_DN, USBH_DP
GPIO_B[27:26]
USB_DN, USB_DP
K8,L7
I/O
GPIO_B[27:26] / USB_DN, USB_DP
GPIO_B[25]
GPIO_B[24] / BM[2]
GPIO_B[23]
GPIO_B[22] / BM[1]
GPIO_B[21] / BM[0]
DAI
DAO
MCLK
LRCK
BCLK
K10
K11
K12
L11
J9
I/O
GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
GPIO_A[24:21] is internally connected with audio CODEC signals.
Refer to Figure 1.3 for more information.
GPIO_B[22:21] have internal pull-down resistor which is
active at power up.
GPIO_B[9]
UT_RX
L9
I/O
GPIO_B[9 ] / UART RX Signal
GPIO_B[8]
UT_TX / SD_nCS
M10
I/O
GPIO_B[8] / UARTTX Signal / DDR SDRAM Chip Select
GPIO_B[7]
ND_nWE
L10
I/O
GPIO_B[7] / Write Enable for NAND Flash
GPIO_B[5:2]
nCS[3:0]
H6, J6
K6, J5
I/O
GPIO_B[5:2] / External Chip Select 3 ~ 0
GPIO_B[1]
SD_nCS / SD_nCLK
L6
I/O
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
SDRAM.
GPIO_B[0]
SD_CKE
J8
I/O
GPIO_B[0] / SDRAM clock control
GPIO_D[19]
FGPIO[12]
H12
I/O
GPIO_D[19] / Fast GPIO bit 12. Internal pull-up resistor is enabled
at reset.
GPIO_D[18]
FGPIO[11]
D2
I/O
GPIO_D[18] / Fast GPIO bit 11. Internal pull-up resistor is enabled at
reset.
GPIO_D[17]
FGPIO[10] / SCL
G2
I/O
GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
GPIO_D[16]
FGPIO[9] / SDA
A9
I/O
GPIO_D[16] / Fast GPIO bit 9 / I2C SDA
GPIO_D[15]
FGPIO[8]
G1
I/O
GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
ADIN_0
G10
AI
General purpose multi-channelADC input 0
ADIN_2
F10
AI
General purpose multi-channelADC input 2
ADIN_4
E10
AI
General purpose multi-channelADC input 4
Clock Pins
XIN
H8
I
Main Crystal Oscillator Input for PLL. 12MHz Crystal
must be used if USB Boot Mode is required. Input
voltage must not exceed VDD_OSC (1.95V max).
XOUT
G9
O
Main Crystal Oscillator Output for PLL
XFILT
G12
AO
PLL filter output
XTIN
K9
I
Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
XTOUT
J10
O
Sub Crystal Oscillator Output
JTAG Interface Pins
TDI
C11
I
JTAG serial data input for ARM940T
TMS
D11
I
JTAG test mode select for ARM940T
TCK
C10
I
JTAG test clock for ARM940T
TDO
D10
I/O
JTAG serial data output for ARM940T. External pull-up resistor
is required to prevent floating during normal operation.
nTRST
B10
I
JTAG reset signal for ARM940T. Active low.
Mode Control Pins
MODE1
B11
I
Mode Setting Input 1. Pull-down for normal operation.
PKG1
J7
I
Package ID1. Pull-up for normal operation.
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