TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-21
Signal Name
Shared Signal
Ball
Type Description – TCC766
USB/UART/IrDA Interface Pins
USB_DP
GPIO_B[26]
P9
I/O
USB Function D+ signal / GPIO_B[26]
USB_DN
GPIO_B[27]
T8
I/O
USB Function D- signal / GPIO_B[27]
USBH_DP
GPIO_B[28]
R10
I/O
USB Host D+ signal / GPIO_B[28]
USBH_DN
GPIO_B[29]
N10
I/O
USB Host D- signal / GPIO_B[29]
UT_TX
GPIO_B[8] / SD_nCS
M11
I/O
UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip
Select
UT_RX
GPIO_B[9]
N11
I/O
UART or IrDARX data / GPIO_B[9]
Audio Interface Pins
BCLK
GPIO_B[21] / BM[0]
N12
I/O
I2S Bit Clock / GPIO_B[21]
Internal pull-down resistor is active at power up.
LRCK
GPIO_B[22] / BM[1]
L14
I/O
I2S Word Clock / GPIO_B[22]
Internal pull-down resistor is active at power up.
MCLK
GPIO_B[23]
N6
I/O
I2S System Clock
DAO
GPIO_B[24] / BM[2]
M14
I/O
I2S Digital Audio data Output
DAI
GPIO_B[25]
M13
I/O
I2S Digital Audio data Input / GPIO_B[25] must be
connected externally to ADCDAT
ADCDAT
K14
O
I2S digital audio data output of audio CODEC(ADC) must
be connected externally to GPIO_B[25] (DAI)
LCH_OUT
H15
AO
DAC Left Channel Output of audio CODEC
RCH_OUT
G15
AO
DAC Right Channel Output of audio CODEC
LOUT
C10
AO
DAC Left Channel Line Output of audio CODEC
ROUT
C8
AO
DAC Right Channel Line Output of audio CODEC
RCH_IN
F1
AI
ADC Right Channel Input of audio CODEC
MIC_IN
A3
AI
Microphone Input of audio CODEC
LCH_IN
G4
AI
ADC Left Channel Input of internal audio CODEC
VMID
A4
AO
Mid-rail reference decoupling point
MICBIAS
C6
AO
Microphone Bias
WMODE
CSB
H1
I
CODEC I/F Control. To enable 2-wire serial interface ot the
internal CODEC, low level must be maintained. This pin
has an internal pull-up resistor.
SDIN
GPIO_A[8] / BW[0]
E7
I
2-Wire MCU Data Input for CODEC
SCLK
GPIO_A[9] / BW[1]
B4
I
2-Wire MCU Clock Input for CODEC
CD DSP Interface Pins
CBCLK
GPIO_A[1]
E11
I/O
CD Data Bit Clock Input / GPIO_A[1]
CLRCK
GPIO_A[2]
E10
I/O
CD Data Word Clock Input / GPIO_A[2]
CDAI
GPIO_A[3]
D9
I/O
CD Data Input / GPIO_A[3]
External Interrupt Pins
EXINT[3]
GPIO_A[15]
D4
I/O
External Interrupt Request [3] / GPIO_A[15]
EXINT[2]
GPIO_A[14] / FGPIO[14]
A1
I/O
External Interrupt Request [2] / GPIO_A[14] / FGPIO[14]
EXINT[1]
GPIO_A[13] / FGPIO[13]
B2
I/O
External Interrupt Request [1] / GPIO_A[13] / FGPIO[13]
EXINT[0]
GPIO_A[12] / FGPIO[12]
E6
I/O
External Interrupt Request [0] / GPIO_A[12] / FGPIO[12]. This pin
is internally connected to the USB2.0 module. Do not use for
external component.
General Purpose I/O Pins
GPIO_A[15]
EXINT[3]
D4
I/O
GPIO_A[15] / External Interrupt Request 3
GPIO_A[14]
EXINT[2] / FGPIO[14]
A1
I/O
GPIO_A[14] / External Interrupt Request 2 / Fast GPIO bit 14
GPIO_A[13]
EXINT[1] / FGPIO[13]
B2
I/O
GPIO_A[13] / External Interrupt Request 1 / Fast GPIO bit 13
GPIO_A[12]
TESTIRQ
E6
I/O
GPIO_A[12] / External Interrupt Request 0 / Fast GPIO bit 12. This
pin is internally connected to the USB2.0 module. Do not use for
external component.
GPIO_A[11]
SDI2 / FGPIO[11] / SCL
C7
I/O
GPIO_A[11] / GSIO2 Data In / Fast GPIO bit 11 / I2C Clock.
GPIO_A[10]
FRM2 / FGPIO[10] / SDA
F8
I/O
GPIO_A[10] / GSIO2 FRM / Fast GPIO bit 10 / I2C Data Line.
GPIO_A[9] / BW[1]
SCLK
B4
I/O
GPIO_A[9] / Bus Width bit 1. The status of BW[1:0] is latched at the
rising edge of nRESET and used to determine external bus width.
Refer to section “MEMORY CONTROLLER” for BW[1:0]
description.
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