Handshake Solutions
HT80C51 User Manual
Peripheral Modules – Standard Serial Interface (SIO0)
Page 38 of 132
© Philips Electronics N.V. 2005
the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to
provide rejection of false start bits. After the 8 data bits and the stop-bit have been received, the result
is loaded into SBUF and RB8, and RI is set to 1, but that is only done, if the following conditions are met:
1.
RI = 0, and
2.
Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions
are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. Then the unit goes
back to looking for a 1-to-0 transition in sio_rxd_i.
5.3.4.6.
More About Modes 2 and 3
These modes are very similar to mode 1, with the main difference, that here 9 data bits are used in-
stead of 8 data bits in mode 0.
11 bits are transmitted (through sio_txd_o) or received (through sio_rxd_i): start bit (0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8 in
SCON) can be assigned the value of 0 or 1. On receive, the 9th data bit goes into RB8 in Special Func-
tion Register SCON, while the stop bit is ignored. In mode 2 the baud rate is programmable to either
1/32 or 1/64 of the clock input sio_clk_i. In mode 3 the baud rate is derived from the overflow rate
of timer 1. [Figure 13] shows a simplified functional diagram of the serial port in modes 2 and 3.
The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in
the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF as a destination register. Transmission
actually commences immediately after the next rollover in the divide-by-16 counter. (Thus, the bit
times are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.) After sending the
start-bit and 9 data bits, the TI bit is set and the stop-bit is sent.
Reception is initiated by the detection of a 1-to-0 transition at sio_rxd_i. For this purpose
sio_rxd_i is sampled at a rate of 16 times whatever baud rate has been established. When a transi-
tion is detected, the divide-by-16 counter is immediately reset, thus it aligns its rollovers with the
boundaries of the incoming bit times. At the 7th, 8th, and 9th counter states of each bit time, the bit
detector samples the value of sio_rxd_i. The value accepted is the value that was seen in at least 2
of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0,
the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to
provide rejection of false start bits. After the 9 data bits and the stop-bit have been received, the result
is loaded into SBUF and RB8, and RI is set to 1, but that is only done, if the following conditions are met:
1.
RI = 0, and
2.
Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions
are met, the first 8 data bits go into SBUF, the 9
th data bit goes into RB8, and RI is activated.
Then the unit goes back to looking for a 1-to-0 transition in sio_rxd_i.
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