HT80C51 User Manual
Peripheral Modules – I2C Interface (SIO1)
Handshake Solutions
© Philips Electronics N.V. 2005
Page 47 of 132
2.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows the data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all re-
ceived bytes other than the last byte. At the end of the last received byte, a “not acknowledge”
is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the I2C bus will not be released.
5.5.4.1.
Modes of Operation
The on-chip SIO1 logic may operate in the following four modes:
1. Master Transmitter mode (not available for slave-only version)
Serial data output through SDA while SCL outputs the serial clock. The first transmitted byte contains
the slave address of the receiving device (7 bits) and the data direction bit. In this mode the data direc-
tion bit (R/W) will be logic 0, and we say that a “W” is transmitted. Thus the first byte transmitted is
SLA+W.
Serial data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is re-
ceived. START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
2. Master Receiver Mode (not available for slave-only version)
The first transmitted byte contains the slave address of the transmitting device (7 bits) and the data
direction bit. In this mode the data direction bit (R/W) will be logic 1, and we say that an “R” is transmit-
ted. Thus the first byte transmitted is SLA+R.
Serial data is received via SDA while SCL outputs the serial clock. Serial data is received 8 bits at a
time. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
output to indicate the beginning and end of a serial transfer.
3. Slave Receiver mode:
Serial data and the serial clock are received through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and
end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit.
4. Slave Transmitter mode:
The first byte is received and handled as in the Slave Receiver mode. However, in this mode, the di-
rection bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA while
the serial clock is input through SCL. START and STOP conditions are recognized as the beginning
and end of a serial transfer.
In a given application, SIO1 may operate as a master and as a slave. In the Slave mode, the SIO1
hardware looks for its own slave address and the general call address. If one of these addresses is
detected, an interrupt is requested. When the microcontroller wishes to become the bus master, the
hardware waits until the bus is free before the Master mode is entered so that a possible slave action
is not interrupted. If bus arbitration is lost in the Master mode, SIO1 switches to the Slave mode im-
mediately and can detect its own slave address in the same serial transfer.
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