R5F2L3ACBNFP datasheet(165/848 Pages) RENESAS

165 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 129 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

9. Clock Generation Circuit

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2

Registers

9.2.1

System Clock Control Register 0 (CM0)

Notes:

1. The CM05 bit stops the XIN clock when high-speed on-chip oscillator mode or low-speed on-chip oscillator mode

is selected. This bit cannot be used to detect whether the XIN clock has stopped. To stop the XIN clock, set the

bits in the following order:

(a) Set bits OCD1 to OCD0 in the OCD register to 00b.

(b) Set the OCD2 bit to 1 (on-chip oscillator clock selected).

2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged.

3. Only when the CM05 bit to 1 (XIN clock stops) and the CM07 bit is set to 1 (XCIN clock), P12_0 and P12_1 can

be used as I/O ports.

4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

5. Change the CM07 bit from 0 to 1 (XCIN clock) after the XCIN clock oscillation has become stable.

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register.

Address 0006h

Bit

b7b6b5

b4b3b2

b1b0

Symbol

CM07

CM06

CM05

CM04

CM03

CM02

CM01

—

After Reset

001

000

Bit

Symbol

Bit Name

Function

R/W

—

Reserved bit

Set to 0.

R/W

CM01 Peripheral function clock stop bit in

wait mode

b1 b0

0 0: Peripheral function clock does not stop in

wait mode

0 1: Clocks f1 to f32 stop in wait mode

1 0: Clocks f1 to f32 and fC stop in wait mode

1 1: Clocks f1 to f32, fC, and fC-LCD stop in wait mode

R/W

CM02

R/W

CM03 XCIN clock stop bit

0: XCIN clock oscillates

1: XCIN clock stops

R/W

CM04 XCIN external clock input enable bit 0: External clock input disabled

1: External clock input enabled

R/W

CM05 XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates

1: XIN clock stops (2)

R/W

CM06 System clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled

1: Divide-by-8 mode

R/W

CM07 XIN and XCIN clock select bit (5)

0: XIN clock

1: XCIN clock

R/W

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