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SH7713 Datasheet(PDF) 115 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 115 Page - Renesas Technology Corp |
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115 / 904 page ![]() Section 3 DSP Operating Unit Rev.1.50 Aug. 30, 2006 Page 75 of 860 REJ09B0288-0150 Bit Bit Name Initial Value R/W Description 11 10 DMY DMX 0 0 R/W R/W Modulo Control Bits Enable or disable modulo addressing for X/Y memory access. These bits can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, these bits are initialized to 0. These bits are not affected in the exception handling state. 9 to 4 For details, refer to section 2, CPU. 3 2 FR1 FR0 0 0 R/W R/W Repeat Flag Bits Used by repeat control instructions. These bits can be modified in privileged mode, privileged DSP mode, or user DSP mode. At reset, these bits are initialized to 0. These bits are not affected in the exception handling state. 1 to 0 For details, refer to section 2, CPU. Note: When data is written to the SR register, 0 should be written to bits that are specified as 0. Repeat Start Register (RS): The repeat start register (RS) holds the start address of a loop repeat module that is controlled by the repeat function. This register can be accessed in DSP mode. At reset, the initial value of this register is undefined. This register is not affected in the exception handling state. Repeat End Register (RE): The repeat end register (RE) holds the end address of a loop repeat module that is controlled by the repeat function. This register can be accessed in DSP mode. At reset, this register is initialized to 0. This register is not affected in the exception handling state. Modulo Register (MOD): The modulo register stores the modulo end address and modulo start address for modulo addressing in upper and lower 16 bits. The upper and lower 16 bits of the modulo register are referred to as the ME register and MS register, respectively. This register can be accessed in DSP mode. At reset, the initial value of this register is undefined. This register is not affected in the exception handling state. The above registers can be accessed by the control register load instruction (LDC) and store instruction (STC). Note that the LDC and STC instructions for the RS, RE, and MOD registers can be used only in privileged DSP mode and user DSP mode. The LDC and STC instruction for the SR register can be executed only when the MD bit is set to 1 or in user DSP mode. Note, however, that the LDC and STC instructions can modify only the RC11 to RC0, RF1 to RF0, DMX, and DMY bits in the SR, as described below. • In user mode, if the LCD and STC instructions are used for the RS, an illegal instruction exception occurs. |
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