SPMCK16Z4MPV16 datasheet(249/500 Pages) FREESCALE

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M68HC16 Z SERIES

MULTICHANNEL COMMUNICATION INTERFACE

USER’S MANUAL

10-9

10.3.4.1 CPHA = 0 Transfer Format

Figure 10-3 is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA

equals zero. Two waveforms are shown for SCK: one for CPOL equal to zero and an-

other for CPOL equal to one. The diagram may be interpreted as a master or slave

timing diagram since the SCK, MISO and MOSI pins are directly connected between

the master and the slave. The MISO signal shown is the output from the slave and the

MOSI signal shown is the output from the master. The SS line is the chip-select input

to the slave.

Figure 10-3 CPHA = 0 SPI Transfer Format

For a master, writing to the SPDR initiates the transfer. For a slave, the falling edge of

SS indicates the start of a transfer. The SCK signal remains inactive for the first half

of the first SCK cycle. Data is latched on the first and each succeeding odd clock edge,

and the SPI shift register is left-shifted on the second and succeeding even clock edg-

es. SPIF is set at the end of the eighth SCK cycle.

When CPHA equals zero, the SS line must be negated and reasserted between each

successive serial byte. If the slave writes data to the SPI data register while SS is as-

serted (low), a write collision error results. To avoid this problem, the slave should read

bit three of PORTMCP, which indicates the state of the SS pin, before writing to the

SPDR again.

12345678

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(FROM MASTER)

MSB

654321

LSB

MSB

LSB

MISO

(FROM SLAVE)

SS (TO SLAVE)

CPHA = 0 SPI TRANSFER

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV16 Datasheet(PDF) 249 Page - Freescale Semiconductor, Inc

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