SPMCK16Z4MPV16 datasheet(256/500 Pages) FREESCALE

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MULTICHANNEL COMMUNICATION INTERFACE

M68HC16 Z SERIES

10-16

USER’S MANUAL

SCCR1 contains a number of SCI configuration parameters, including transmitter and

receiver enable bits, interrupt enable bits, and operating mode enable bits. The

CPU16 can read and write this register at any time. The SCI can modify the RWU bit

under certain circumstances.

Changing the value of SCI control bits during a transfer may disrupt operation. Before

changing register values, allow the SCI to complete the current transfer, then disable

the receiver and transmitter.

10.4.1.2 SCI Status Register

The SCSR contains flags that show SCI operating conditions. These flags are cleared

either by SCI hardware or by a read/write sequence. To clear SCI transmitter flags,

read the SCSR and then write to the SCDR. To clear SCI receiver flags, read the

SCSR and then read the SCDR. A long-word read can consecutively access both the

SCSR and the SCDR. This action clears receiver status flag bits that were set at the

time of the read, but does not clear TDRE or TC flags.

If an internal SCI signal for setting a status bit comes after the CPU has read the as-

serted status bits, but before the CPU has written or read the SCDR, the newly set sta-

tus bit is not cleared. The SCSR must be read again with the bit set, and the SCDR

must be written to or read before the status bit is cleared.

Reading either byte of the SCSR causes all 16 bits to be accessed, and any status bit

already set in either byte will be cleared on a subsequent read or write of the SCDR.

10.4.1.3 SCI Data Register

The SCDR contains two data registers at the same address. The RDR is a read-only

the receive serial shifter and is transferred to the RDR. The TDR is a write-only register

that contains data to be transmitted. The data is first written to the TDR, then trans-

ferred to the transmit serial shifter, where additional format bits are added before

transmission.

10.4.2 SCI Pins

Four pins are associated with the SCI: TXDA, TXDB, RXDA, and RXDB. The state of

the TE or RE bit in SCI control register 1 of each SCI submodule (SCCR1A, SCCR1B)

determines whether the associated pin is configured for SCI operation or general-pur-

pose I/O. The MDDR assigns each pin as either input or output. The WOMC bit in

SCCR1A or SCCR1B determines whether the associated RXD and TXD pins, when

configured as outputs, function as open-drain output pins or normal CMOS outputs.

The MDDR and WOMC assignments are valid regardless of whether the pins are con-

figured for SPI use or general-purpose I/O.

SCI pins are listed in Table 10-5.

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV16 Datasheet(PDF) 256 Page - Freescale Semiconductor, Inc

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