SPMCK16Z4MPV16 datasheet(143/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-37

Descriptions are made in terms of individual system clock states, labelled {S0, S1,

S2,..., SN}. The designation “state” refers to the logic level of the clock signal, and

does not correspond to any implemented machine state. A clock cycle consists of two

successive states. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for

more information on clock control timing.

Bus cycles terminated by DSACK assertion normally require a minimum of three

CLKOUT cycles. To support systems that use CLKOUT to generate DSACK and other

inputs, asynchronous input setup time and asynchronous input hold times are speci-

fied. When these specifications are met, the MCU is guaranteed to recognize the ap-

propriate signal on a specific edge of the CLKOUT signal.

5.6.2 Regular Bus Cycle

The following paragraphs contain a discussion of cycles that use external bus control

logic. Refer to 5.6.3 Fast Termination Cycles for information about fast termination

cycles.

To initiate a transfer, the MCU asserts an address and the SIZ[1:0] signals. The SIZ

signals and ADDR0 are externally decoded to select the active portion of the data bus.

Refer to 5.5.2 Dynamic Bus Sizing. When AS, DS, and R/W are valid, a peripheral

device either places data on the bus (read cycle) or latches data from the bus (write

cycle), then asserts a DSACK[1:0] combination that indicates port size.

The DSACK[1:0] signals can be asserted before the data from a peripheral device is

valid on a read cycle. To ensure valid data is latched into the MCU, a maximum period

between DSACK assertion and DS assertion is specified.

There is no specified maximum for the period between the assertion of AS and

DSACK. Although the MCU can transfer data in a minimum of three clock cycles when

the cycle is terminated with DSACK, the MCU inserts wait cycles in clock period incre-

ments until either DSACK signal goes low.

If bus termination signals remain unasserted, the MCU will continue to insert wait

states, and the bus cycle will never end. If no peripheral responds to an access, or if

an access is invalid, external logic should assert the BERR or HALT signals to abort

the bus cycle (when BERR and HALT are asserted simultaneously, the CPU16 acts

as though only BERR is asserted). When enabled, the SIM bus monitor asserts BERR

when DSACK response time exceeds a predetermined limit. The bus monitor time-out

period is determined by the BMT[1:0] field in SYPCR. The maximum bus monitor time-

out period is 64 system clock cycles.

5.6.2.1 Read Cycle

During a read cycle, the MCU transfers data from an external memory or peripheral

device. If the instruction specifies a long-word or word operation, the MCU attempts to

read two bytes at once. For a byte operation, the MCU reads one byte. The portion of

the data bus from which each byte is read depends on operand size, peripheral ad-

dress, and peripheral port size. Figure 5-12 is a flowchart of a word read cycle. Refer

to 5.5.2 Dynamic Bus Sizing, 5.5.4 Misaligned Operands, and the

SIM Reference

Manual (SIMRM/AD) for more information.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

SPMCK16Z4MPV16 Datasheet(PDF) 143 Page - Freescale Semiconductor, Inc

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