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SPMCK16Z4MPV16 Datasheet(PDF) 147 Page - Freescale Semiconductor, Inc

Part # SPMCK16Z4MPV16
Description  M68HC16Z Series
PDF  500 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

SPMCK16Z4MPV16 Datasheet(HTML) 147 Page - Freescale Semiconductor, Inc

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M68HC16 Z SERIES
SYSTEM INTEGRATION MODULE
USER’S MANUAL
5-41
Figure 5-14 CPU Space Address Encoding
5.6.4.1 Breakpoint Acknowledge Cycle
Breakpoints stop program execution at a predefined point during system development.
In M68HC16 Z-series MCUs, breakpoints are treated as a type of exception process-
ing. Breakpoints can be used alone or in conjunction with background debug mode.
M68HC16 Z series MCUs have only one source and type of breakpoint. This is a hard-
ware breakpoint initiated by assertion of the BKPT input. Other modular microcontrol-
lers may have more than one source or type. The breakpoint acknowledge cycle
discussed here is the bus cycle that occurs as a part of breakpoint exception process-
ing when a breakpoint is initiated while background debug mode is not enabled.
BKPT is sampled on the same clock phase as data. BKPT is valid, the data is tagged
as it enters the CPU16 pipeline. When BKPT is asserted while data is valid during an
instruction prefetch, the acknowledge cycle occurs immediately after that instruction
has executed. When BKPT is asserted while data is valid during an operand fetch, the
acknowledge cycle occurs immediately after execution of the instruction during which
it is latched. If BKPT is asserted for only one bus cycle and a pipe flush occurs before
BKPT is detected by the CPU16, no acknowledge cycle occurs. To ensure detection,
BKPT should be asserted until a breakpoint acknowledge cycle is recognized.
When BKPT assertion is acknowledged by the CPU16, the MCU performs a word read
from CPU space address $00001E. This corresponds to the breakpoint number field
(ADDR[4:2]) and the type bit (T) being set to all ones (source 7, type 1). If this bus cycle
is terminated by BERR or by DSACK, the MCU performs breakpoint exception pro-
cessing. Refer to Figure 5-15 for a flowchart of the breakpoint operation. Refer to the
SIM Reference Manual (SIMRM/AD) for further information.
CPU SPACE CYC TIM
0000000000000000000
T0
BKPT#
19
23
16
000000111111111111111110
19
16
23
111
111
11111111111111111111
1
111
LEVEL
19
16
23
CPU SPACE CYCLES
FUNCTION
CODE
20
20
20
0
0
0
CPU SPACE
TYPE FIELD
ADDRESS BUS
BREAKPOINT
ACKNOWLEDGE
LOW POWER
STOP BROADCAST
INTERRUPT
ACKNOWLEDGE
2
41
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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