PIC18LF4331 datasheet(243/392 Pages) MICROCHIP

243 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 243

PIC18F2331/2431/4331/4431

ADCON3: A/D CONTROL REGISTER 3

R/W-0

U-0

R/W-0

ADRS1

ADRS0

—

SSRC4(1)

SSRC3(1)

SSRC2(1)

SSRC1(1)

SSRC0(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

ADRS<1:0>

: A/D Result Buffer Depth Interrupt Select Control for Continuous Loop Mode bits

The ADRS bits are ignored in Single-Shot mode.

= Interrupt is generated when each word is written to the buffer

= Interrupt is generated when the 2nd and 4th words are written to the buffer

= Interrupt is generated when the 4th word is written to the buffer

= Unimplemented

bit 5

Unimplemented:

Read as ‘0’

bit 4-0

SSRC<4:0>:

A/D Trigger Source Select bits(1)

00000

= All triggers disabled

xxxx1

= External interrupt RC3/INT0 starts A/D sequence

xxx1x

= Timer5 starts A/D sequence

xx1xx

= Input Capture 1 (IC1) starts A/D sequence

x1xxx

= CCP2 compare match starts A/D sequence

1xxxx

= Power Control PWM module rising edge starts A/D sequence

Note 1:

The SSRC<4:0> bits can be set such that any of the triggers will start a conversion (e.g., SSRC<4:0> = 00101

will trigger the A/D conversion sequence when RC3/INT0 or Input Capture 1 event occurs).

PIC18LF4331 Datasheet(PDF) 243 Page - Microchip Technology

PIC18LF4331 Datasheet(HTML) 243 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL