PIC18LF4331 datasheet(246/392 Pages) MICROCHIP

246 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 246

 2010 Microchip Technology Inc.

The A/D channels are grouped into four sets of 2 or

3 channels. For the PIC18F2331/2431 devices, AN0

and AN4 are in Group A, AN1 is in Group B, AN2 is in

Group C and AN3 is in Group D. For the PIC18F4331/

4431 devices, AN0, AN4 and AN8 are in Group A, AN1

and AN5 are in Group B, AN2 and AN6 are in Group C

and AN3 and AN7 are in Group D. The selected chan-

nel in each group is selected by configuring the A/D

Channel Select Register, ADCHS.

The analog voltage reference is software selectable to

either the device’s positive and negative analog supply

voltage (AVDD and AVSS), or the voltage level on the

RA3/AN3/VREF+/CAP2/QEA

and

RA2/AN2/VREF-/

CAP1/INDX, or some combination of supply and

external sources. Register ADCON1 controls the

voltage reference settings.

The A/D Converter has a unique feature of being able

to operate while the device is in Sleep mode. To

operate in Sleep, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted.

Each port pin associated with the A/D Converter can

individually be configured as an analog input or digital

I/O using the ANSEL0 and ANSEL1 registers. The

ADRESH and ADRESL registers contain the value in

the result buffer pointed to by ADPNT<1:0>

(ADCON1<1:0>). The result buffer is a 4-deep circular

buffer that has a Buffer Empty status bit, BFEMT

(ADCON1<3>), and a Buffer Overflow status bit,

BFOVFL (ADCON1<2>).

FIGURE 21-1:

A/D BLOCK DIAGRAM

ADRESH, ADRESL

VREF+

AVSS(2)

AVDD(2)

ADC

AN0

AN4

S/H-1

S/H-2

VREF-

Analog

MUX

Analog

MUX

AN8(1)

AN2/VREF-

AN6(1)

Seq.

Cntrl.

MUX

4x10-Bit FIFO

VCFG<1:0>

VREFL

VREFH

ACMOD<1:0>,

AVSS(2)

AVSS

ADPNT<1:0>

ACMOD<1:0>,

AN1

AN5(1)

AN3/VREF+

AN7(1)

ACONV

ACSCH

ACMODx

Note

AN5 through AN8 are available only on PIC18F4331/4431 devices.

I/O pins have diode protection to VDD and VSS.

GxSEL<1:0>

S/H

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