PIC18LF4331 datasheet(248/392 Pages) MICROCHIP

248 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 248

 2010 Microchip Technology Inc.

21.1.3

CONVERSION SEQUENCING

The ACMOD<1:0> bits control the sequencing of the

A/D conversions. When ACSCH = 0, the A/D is

configured to sample and convert a single channel.

The ACMOD bits select which group to perform the

conversions and the GxSEL<1:0> bits select which

channel in the group is to be converted. If Single-Shot

mode is enabled, the A/D interrupt flag will be set after

the channel is converted. If Continuous Loop mode is

enabled, the A/D interrupt flag will be set according to

the ADRS<1:0> bits.

When ACSCH = 1, multiple channel sequencing is

enabled and two submodes can be selected. The first

mode is Sequential mode with two settings. The first set-

ting is called SEQM1, and first samples and converts the

selected Group A channel, and then samples and

converts the selected Group B channel. The second

mode is called SEQM2, and it samples and converts a

Group A channel, Group B channel, Group C channel

and finally, a Group D channel.

The second multiple channel sequencing submode is

Simultaneous Sampling mode. In this mode, there are

also two settings. The first setting is called STNM1, and

uses the two sample and hold circuits on the A/D

module. The selected Group A and B channels are

simultaneously sampled and then the Group A channel

is converted followed by the conversion of the Group B

channel. The second setting is called STNM2, and

starts the same as STNM1, but follows it with a

simultaneous sample of Group C and D channels. The

A/D module will then convert the Group C channel

followed by the Group D channel.

21.1.4

TRIGGERING A/D CONVERSIONS

The PIC18F2331/2431/4331/4431 devices are capable

of triggering conversions from many different sources.

The same method used by all other microcontrollers of

setting the GO/DONE bit still works. The other trigger

sources are:

• RC3/INT0 Pin

• Timer5 Overflow

• Input Capture 1 (IC1)

• CCP2 Compare Match

• Power Control PWM Rising Edge

These triggers are enabled using the SSRC<4:0> bits

(ADCON3<4:0>). Any combination of the five sources

can trigger a conversion by simply setting the corre-

sponding bit in ADCON3. When the trigger occurs, the

GO/DONE bit is automatically set by the hardware and

then cleared once the conversion completes.

21.1.5

A/D MODULE INITIALIZATION

STEPS

The following steps should be followed to initialize the

A/D module:

Configure the A/D module:

Configure the analog pins, voltage reference

and digital I/O.

b) Select the A/D input channels.

Select the A/D Auto-Conversion mode

(Single-Shot or Continuous Loop).

d) Select the A/D conversion clock.

e) Select the A/D conversion trigger.

Configure the A/D interrupt (if required):

a) Set the GIE bit.

b) Set the PEIE bit.

Set the ADIE bit.

d) Clear the ADIF bit.

e) Select the A/D trigger setting.

Select the A/D interrupt priority.

Turn on ADC:

a) Set the ADON bit in the ADCON0 register.

b) Wait the required power-up setup time,

about 5-10

s.

Start the sample/conversion sequence:

a) Sample for a minimum of 2 TAD and start

the conversion by setting the GO/DONE bit.

The GO/DONE bit is set by the user in

software or by the module if initiated by a

trigger.

b) If TACQ is assigned a value (multiple of TAD),

then setting the GO/DONE bit starts a

sample period of the TACQ value, then starts

a conversion.

Wait

for

A/D

conversion/conversions

complete using one of the following options:

a) Poll for the GO/DONE bit to be cleared if in

Single-Shot mode.

b) Wait for the A/D Interrupt Flag (ADIF) to be

set.

Poll for the BFEMT bit to be cleared to

signify that at least the first conversion has

completed.

Read the A/D results, clear the ADIF flag,

reconfigure the trigger.

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