PIC18LF4331 datasheet(252/392 Pages) MICROCHIP

252 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 252

 2010 Microchip Technology Inc.

21.7

Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT<3:0> and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the power-managed mode clock that

will be used. After the power-managed mode is entered

(either of the power-managed Run modes), an A/D

acquisition or conversion may be started. Once an

acquisition or conversion is started, the device should

continue to be clocked by the same power-managed

mode clock source until the conversion has been com-

pleted. If desired, the device may be placed into the

corresponding power-managed Idle mode during the

conversion.

If the power-managed mode clock frequency is less

than 1 MHz, the A/D RC clock source should be

selected.

Operation in Sleep mode requires the A/D RC clock to

be selected. If bits, ACQT<3:0>, are set to ‘0000’ and

a conversion is started, the conversion will be delayed

one instruction cycle to allow execution of the SLEEP

instruction and entry to Sleep mode. The IDLEN and

SCS bits in the OSCCON register must have already

been cleared prior to starting the conversion.

21.8

Configuring Analog Port Pins

The ANSEL0, ANSEL1, TRISA and TRISE registers all

configure the A/D port pins. The port pins needed as

analog inputs must have their corresponding TRIS bits

set (input). If the TRIS bit is cleared (output), the digital

output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

ANSEL0, ANSEL1 and TRIS bits.

Note:

The A/D can operate in Sleep mode only

when configured for Single-Shot mode. If

the part is in Sleep mode, and it is possible

for a source other than the A/D module to

wake the part, the user must poll

ADCON0<GO/DONE> to ensure it is clear

before reading the result.

Note 1:

When reading the PORT register, all pins

configured as analog input channels will

read as cleared (a low level). Pins

configured as digital inputs will convert an

analog input. Analog levels on a digitally

configured input will be accurately

converted.

Analog levels on any pin defined as a

digital input may cause the digital input

buffer to consume current out of the

device’s specification limits.

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