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PIC18LF4331 Datasheet(PDF) 254 Page - Microchip Technology |
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PIC18LF4331 Datasheet(HTML) 254 Page - Microchip Technology |
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254 / 392 page ![]() PIC18F2331/2431/4331/4431 DS39616D-page 254 2010 Microchip Technology Inc. 21.9.1 A/D RESULT REGISTER The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16 bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 21-5 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’s. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers. FIGURE 21-5: A/D RESULT JUSTIFICATION EQUATION 21-3: CONVERSION TIME FOR MULTI-CHANNEL MODES 10-Bit Result ADRESH ADRESL 0000 00 ADFM = 0 0 2 1 0 7 7 10-Bit Result ADRESH ADRESL 10-Bit Result 0000 00 7 0 7 6 5 0 ADFM = 1 Right Justified Left Justified Sequential Mode: Simultaneous Mode: T = (TACQ)A + (TCON)A + [(TACQ)B – 12 TAD] + (TCON)B + [(TACQ)C – 12 TAD] + (TCON)C + [(TACQ)D – 12 TAD] + (TCON)D T = TACQ + (TCON)A + (TCON)B + TACQ + (TCON)C + (TCON)D |
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