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PIC18LF4331 Datasheet(PDF) 253 Page - Microchip Technology

Part # PIC18LF4331
Description  28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
PDF  392 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18LF4331 Datasheet(HTML) 253 Page - Microchip Technology

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 2010 Microchip Technology Inc.
DS39616D-page 253
PIC18F2331/2431/4331/4431
21.9
A/D Conversions
Figure 21-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins. The internal A/D
RC oscillator must be selected to perform a conversion
in Sleep.
Figure 21-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<3:0>
bits are set to ‘010’ and a 4 TAD acquisition time is
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The resulting buffer loca-
tion will contain the partially completed A/D conversion
sample. This will not set the ADIF flag, therefore, the
user must read the buffer location before a conversion
sequence overwrites it.
After the A/D conversion is completed or aborted, a
2TAD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 21-3:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 21-4:
A/D CONVERSION TAD CYCLES (ACQT<3:0> = 0010, TACQ = 4 TAD)
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8
TAD11
TAD9 TAD10
GO/DONE bit cleared on the rising edge of Q1 after the first Q3
Conversion Starts
b2
b8
b7
b6
b5
b4
b3
b9
b1
b0
following TAD11 and result buffer is loaded.(1)
GO/DONE bit is
set and holding
cap is
disconnected
from analog
input
Note 1:
Conversion time is a minimum of 11 TAD + 2 TCY and a maximum of 11 TAD + 6 TCY.
A/D Triggered
(Holding capacitor is disconnected)
1
2
3
4
TACQT Cycles
Automatic
Acquisition
Time
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8
TAD11
TAD9 TAD10
GO/DONE bit cleared on the rising edge of Q1 after the first Q3
Conversion Starts
b2
b8
b7
b6
b5
b4
b3
b9
b1
b0
following TAD11 and result buffer is loaded.(1)
TAD Cycles
Note 1:
In Continuous modes, next conversion starts at the end of TAD12.



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